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integrated precision battery sensor for automotive preliminary technical data aduc7030/aduc7033 features high precision adcs dual channel, simultaneous sampling, 16-bit ? adcs programmable adc throughput from 1 hz to 8 khz on-chip 5ppm/c voltage reference current channel fully differential, buffered input programmable gain from 1 to 512 adc input range: ?200 mv to +300 mv digital comparators, with current accumulator feature voltage channel buffered, on-chip attenuator for 12v battery inputs temperature channel external and on-chip temperature sensor options microcontroller arm7tdmi core, 16-/32-bit risc architecture 20.48 mhz pll with programmable divider pll input source on-chip precision oscillator on-chip low-power oscillator external (32.768 khz) watch crystal jtag port supports code download and debug memory 32 kbytes flash/ee memory, 4 kbytes sram (aduc7030) 96 kbytes flash/ee memory, 6 kbytes sram (aduc7033) 10 kcycles flash/ee endurance, 20 years flash/ee retention in-circuit download via jtag and lin on-chip peripherals lin 2.0 (slave) compatible support via uart with hardware synchronization flexible wake-up i/o pin, master/slave spi serial i/o 9-pin gpio port, 3 x general purpose timers wake-up and watchdog timers power supply monitor, on-chip power-on-reset power operates directly from 12 v battery supply current consumption normal mode 10 ma at 10 mhz low power monitor mode packages and temperature range 48 pin lfcsp 7x7 mm or 48 pin lqfp 7x7 mm body package fully specified for ?40c to +115c operation applications battery sensing/management for automotive systems functional block diagram 05994-001 16-bit - ? adc pga iin+ iin? result accumulator digital comparator 16-bit - ? adc mux buf tc k tdi tdo ntrst tms vdd reg_avdd reg_dvdd agnd dgnd vss io_vss gpio_0 gpio_1 gpio_2 gpio_3 gpio_4 gpio_5 gpio_6 gpio_7 gpio_8 vbat vtemp gnd_sw vref precision analog acquisition arm7tdmi mcu 20mhz precision osc low power osc on-chip pll xtal1 xtal2 3 timers wdt w/u timer gpio port uart port spi port lin wu sti lin/bsd 2.6v ldo psm por memory 32kb flash 4kb ram reset temperature sensor precision reference aduc7030/aduc7033 figure 1. rev. p re information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved.
aduc7030/aduc7033 preliminary technical data rev. pre | page 2 of 150 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 specifications..................................................................................... 6 electrical specifications............................................................... 6 timing specifications ................................................................ 12 spi timing specifications ..................................................... 12 lin timing specifications .................................................... 16 terminology .................................................................................... 17 absolute maximum ratings.......................................................... 18 esd caution................................................................................ 18 pin configuration and function descriptions........................... 19 theory of operation ...................................................................... 22 overview of the arm7tdmi core.......................................... 22 thumb mode (t) ................................................................... 22 multiplier (m)......................................................................... 22 embeddedice (i) ................................................................... 22 arm7 exceptions .................................................................. 23 arm registers ........................................................................ 23 interrupt latency.................................................................... 23 memory organisation ............................................................... 24 memory format ..................................................................... 24 sram....................................................................................... 24 remap ...................................................................................... 24 remap oper ation ................................................................... 25 sysmap0 register:................................................................ 25 aduc7030/aduc7033 reset................................................... 26 rststa register: ................................................................... 26 rstclr register:................................................................... 26 flash/ee memory and the aduc7030/aduc7033 .............. 27 (1) serial downloading (in-circuit programming).......... 27 (2) jtag access....................................................................... 27 aduc7030 flash/ee memory ............................................. 27 aduc7033 flash/ee memory ............................................. 27 aduc7030 flash/ee control interface .................................. 27 fee0con register: ............................................................... 28 command sequence for executing a mass erase.............. 29 fee0sta register: ................................................................. 29 fee0mod register: .............................................................. 30 fee0adr registers: .............................................................. 30 fee0dat registers................................................................ 30 aduc7030 flash/ee memory security................................... 31 flash/ee memory protection registers: ............................. 31 sequence to write the key and set permanent protection .................................................................................................. 32 aduc7033 flash/ee control interface .................................. 32 fee0con and fee1con registers: .................................. 33 command sequence for executing a mass erase .............. 34 fee0sta and fee1sta registers: ...................................... 34 fee0adr and fee1adr registers: ................................... 35 fee0dat and fee1dat registers: .................................... 35 fee0mod and fee1mod registers: ................................ 35 aduc7033 flash/ee memory security .................................. 36 block0, flash/ee memory protection registers: ............... 36 block1, flash/ee memory protection registers: ............... 37 sequence to write the key and set permanent protection: .................................................................................................. 38 flash/ee memory reliability.................................................... 38 code execution time from sram and flash/ee ................ 39 execution from sram .......................................................... 39 execution from flash/ee ...................................................... 39 aduc7030/aduc7033 kernel ................................................ 40 memory mapped registers ....................................................... 42 16-bit ?? analog to digital converters ............................... 48 current channel adc (i-adc).......................................... 48
preliminary technical data aduc7030/aduc7033 rev. pre| page 3 of 150 voltage/temperature channel adc (v/t-adc) ..................50 adc ground switch ..................................................................51 adc noise performance tables ...............................................52 adc mmr interface ..................................................................53 adc status register: ..............................................................53 adc interrupt mask register:..............................................55 adc mode register: ..............................................................55 current channel adc control register:............................57 voltage/temperature channel adc control register:.....58 adc filter register: ...............................................................59 adc configuration register: ...............................................61 current channel adc data register: .................................62 voltage channel data register: ............................................62 temperature channel adc data register:.........................62 current channel adc offset calibration register:..........62 voltage channel offset calibration register: .....................63 temperature channel offset calibration register:............63 current channel adc gain calibration register: ............63 voltage channel gain calibration register: .......................64 temperature channel gain calibration register:..............64 current channel adc result counter limit register: ....64 current channel adc result count register:...................64 current channel adc threshold register:........................65 current channel adc threshold count limit register:.65 current channel adc threshold count register: ...........65 current channel adc accumulator register:...................65 low power voltage reference scaling factor .....................66 adc power modes of operation..............................................66 adc startup procedure .........................................................66 adc normal power mode ....................................................66 adc low power mode ..........................................................66 adc low power-plus mode .................................................67 adc comparator and accumulator......................................67 adc sinc3 digital filter response ......................................67 adc calibration.....................................................................69 using the offset and gain calibration ................................70 understanding the offset and gain calibration registers70 adc diagnostics ........................................................................71 current adc diagnostics .....................................................71 voltage/temperature adc diagnostics ..............................71 power supply support circuits .....................................................72 aduc7030/aduc7033 system clocks........................................73 pllsta register: ....................................................................74 pllcon pre-write key pllkey0:......................................75 pllcon pre-write key pllkey1:......................................75 pllcon register: ..................................................................75 powcon pre-write key powkey0: ................................75 powcon pre-write key powkey1: ................................75 powcon register: ...............................................................76 aduc7030/ aduc7033 low power clock calibration........77 osc0trm register:...............................................................78 osc0con register:...............................................................78 osc0sta register:.................................................................79 osc0val0 register: ..............................................................79 osc0val1 register: ..............................................................79 processor reference peripherals ...................................................80 interrupt system..........................................................................80 irq............................................................................................81 fiq ............................................................................................81 timers...............................................................................................82 timer0life-time timer ..........................................................83 timer0 value register:...........................................................83 timer0 capture register: ......................................................83 timer0 control register:.......................................................84 timer0 load registers: ..........................................................85 timer0 clear register: ...........................................................85
aduc7030/aduc7033 preliminary technical data rev. pre | page 4 of 150 timer1.......................................................................................... 86 timer1 load registers:.......................................................... 86 timer1 clear register:........................................................... 86 timer1 value register: .......................................................... 86 timer1 capture register: ...................................................... 87 timer1 control register: ...................................................... 87 timer2 - wake-up timer ......................................................... 88 timer2 load registers:.......................................................... 88 timer2 clear register:........................................................... 88 timer2 value register: .......................................................... 88 timer2 control register: ...................................................... 89 timer3 - watchdog timer ........................................................ 90 timer3 load register: ........................................................... 90 timer3 value register: .......................................................... 91 timer3 clear register:........................................................... 91 timer3 control register: ...................................................... 91 timer4 - sti timer .................................................................... 92 timer4 load registers:.......................................................... 92 timer4 clear register:........................................................... 92 timer4 value register: .......................................................... 92 timer4 capture register: ...................................................... 92 timer4 control register: ...................................................... 93 general purpose i/o ...................................................................... 94 gpio port0 control register: .............................................. 96 gpio port1 control register: .............................................. 97 gpio port2 control register: .............................................. 98 gpio port0 data register:.................................................... 99 gpio port1 data register:.................................................. 100 gpio port2 data register:.................................................. 101 gpio port0 set register:..................................................... 102 gpio port1 set register:..................................................... 103 gpio port2 set register:..................................................... 104 gpio port0 clear register:................................................. 105 gpio port1 clear register:................................................. 106 gpio port2 clear register:................................................. 107 high voltage peripheral control interface ............................... 108 high voltage interface control register:.......................... 109 high voltage data register:................................................ 110 high voltage configuration0 register:............................. 111 high voltage configuration1 register:............................. 112 high voltage monitor register: ......................................... 113 high voltage status register: ............................................. 114 wake-up (wu)........................................................................ 115 wake-up (wu) pin circuit description.......................... 115 handling interrupts from the high voltage peripheral control interface ...................................................................... 116 low voltage flag (lvf)........................................................... 116 high voltage diagnostics........................................................ 116 uart serial interface ...................................................... 117 baud rate generation.............................................................. 117 normal 450 uart baud rate generation ....................... 117 aduc7030/aduc7033 fractional divider: ..................... 117 uart register definition....................................................... 118 uart tx register: .............................................................. 118 uart rx register: .............................................................. 118 uart divisor latch register 0:......................................... 118 uart divisor latch register 1:......................................... 118 uart control register 0: ................................................... 119 uart control register 1: ................................................... 120 uart status register 0: ...................................................... 121 uart interrupt enable register 0:.................................... 122 uart interrupt identification register 0:........................ 122 uart fractional divider register: ................................... 123 serial peripheral interface ........................................ 124 spi control register: ........................................................... 125 spi status register:............................................................... 126 spi receive register:............................................................ 126
preliminary technical data aduc7030/aduc7033 rev. pre | page 5 of 150 spi transmit register:......................................................... 126 spi divider register: ........................................................... 127 serial test interface ...................................................................... 128 sti key0 register:................................................................ 128 sti key1 register:................................................................ 128 sti data0 register: ........................................................... 128 sti data1 register: ........................................................... 129 sti data2 register: ........................................................... 129 sti control register:........................................................... 129 serial test interface output structure .............................. 130 using the serial test interface............................................ 130 lin (local interconnect network) interface.............. 132 lin mmr description............................................................ 132 lin hardware synchronization status register: ............. 133 lin hardware synchronization control register 0:....... 134 lin hardware synchronization control register 1:....... 136 lin hardware synchronization timer0 register:........... 136 lin hardware break timer1 register: ............................. 137 lin hardware interface .......................................................... 137 lin frame protocol............................................................. 137 lin frame break symbol ................................................... 137 lin frame synchronization byte ...................................... 137 lin frame protected identifier.......................................... 137 lin frame data byte........................................................... 137 lin frame data transmission and reception ................ 138 example lin hardware synchronization routine.......... 139 lin diagnostics ................................................................... 140 lin operation during thermal shutdown.......................140 bit serial device (bsd) interface................................................141 bsd communication hardware interface ............................141 bsd related mmrs ..................................................................142 lin hardware synchronization capture register: ..........142 lin hardware synchronization compare register: ........142 bsd communications frame .................................................143 bsd example pulse widths.................................................143 typical bsd program flow .................................................143 bsd data reception .................................................................144 bsd data transmission ...........................................................144 wake-up from bsd interface .................................................144 aduc7030/aduc7033 on-chip diagnostics .........................145 adc diagnostics ......................................................................145 internal test voltage.............................................................145 internal short mode .............................................................145 internal current sources .....................................................145 high voltage i/o diagnostics .............................................145 high voltage current detection.........................................145 part identification .........................................................................146 system serial id register 0:.................................................146 system serial id register 1:.................................................147 system kernel checksum: ...................................................147 system identification fee0adr: .......................................148 aduc7030/aduc7033 example schematic.............................149 outline dimensions......................................................................150 ordering guide .........................................................................150
preliminary technical data aduc7030/aduc7033 specifications electrical specifications v dd = 3.5 v to 18 v, v ref = 1.2 v internal reference, f core = 10.24 mhz driven from external 32.768 khz watch crystal or on-chip precision oscillator, all specifications t a = ?40c to 115c, unless otherwise noted. table 1. aduc7030/aduc7033 specifications parameter test conditions/comments min typ max unit adc specifications conversion rate 1 chop off, adc normal operating mode 4 8000 hz chop on, adc normal operating mode 4 2600 hz chop on, adc low power mode 1 650 hz current channel no missing codes 1 valid for all adc update rates and adc modes 16 bits integral nonlinearity 1 , 2 10 60 ppm of fsr offset error 2, 3, 4,5 chop off, 1 lsb = (36.6/gain) v ?10 3 +10 lsb offset error 1, 3, 6 chop on ?2 0.5 +2 v offset error drift 6 chop off, valid for adc gains of 4 to 64, normal mode 0.03 lsb/c offset error drift 6 chop off, valid for adc gains of 128 to 512, normal mode 30 nv/c offset error drift 6 chop on 10 nv/c total gain error , 1, 3, 7, 8, 9 , 10 normal mode ?0.5 0.1 +0.5 % total gain error 1, 3, 7, 9, 11 low power mode ?4 0.2 +4 % total gain error 1, 3, 7, 9, 12 low power-plus mode, using precision v ref ?1 0.2 +1 % gain drift 3 ppm/c pga gain mismatch error 0.1 % output noise 1, 13 4 hz update rate, gain = 512, chop enabled 60 90 nv rms 10 hz update rate, gain = 512, chop enabled 100 150 nv rms 1 khz update rate, gain = 512 0.6 0.9 v rms 1 khz update rate, gain = 32 0.8 1.2 v rms 1 khz update rate, gain = 4 2.0 2.8 v rms 8 khz update rate, gain = 32 2.5 3.5 v rms 8 khz update rate, gain = 4 14 21 v rms adc low power mode, fadc = 10 hz, gain = 128 1.25 1.9 v rms adc low power mode, fadc = 1 hz, gain = 128 0.35 0.5 v rms adc low power-plus mode, fadc = 1 hz, gain = 512 0.1 0.15 v rms voltage channel 14 no missing codes 1 valid at all adc update rates 16 bits integral nonlinearity 1 10 60 ppm of fsr offset error 3, 5 chop off , 1 lsb 16 = 439.5 v ?10 1 +10 lsb offset error 1, 3 chop on 0.3 1 lsb offset error drift chop off 0.03 lsb/c total gain error 1, 3, 7, 15, 10 includes resistor mismatch ?0.25 0.06 +0.25 % total gain error 1, 3, 7, 15, 10 temperature range = ?25c to +65c ?0.15 0.03 +0.15 % gain drift includes resistor mismatch drift 3 ppm/c output noise 1, 16 4 hz update rate 60 90 v rms 10 hz update rate 60 90 v rms 1 khz update rate 180 270 v rms 8 khz update rate 1600 2400 v rms
preliminary technical data aduc7030/aduc7033 rev. pre | page 7 of 150 parameter test conditions/comments min typ max unit temperature channel no missing codes 1 valid at all adc update rates 16 bits integral nonlinearity 1 10 60 ppm of fsr offset error 3, 5, 17, 18 chop off , 1 lsb16=19.84uv ?10 3 +10 lsb offset error 1, 3 chop on ?5 1 5 lsb offset error drift chop off 0.03 lsb/c total gain error ,1, 3, 19 ?0.2 0.06 +0.2 % gain drift 3 ppm/c output noise 1 1 khz update rate 7.5 11.25 v rms adc specifications analog input internal v ref = 1.2 v current channel absolute input voltage range applies to both iin+ and iin? ?200 +300 mv input voltage range 20,21 gain = 1 22 1.2 v gain = 2 22 600 mv gain = 4 22 300 mv gain = 8 150 mv gain = 16 75 mv gain = 32 37.5 mv gain = 64 18.75 mv gain = 128 9.375 mv gain = 256 4.68 mv gain = 512 2.3 mv input leakage current 1 ?3 +3 na input offset current 1, 23 0.5 1.5 na voltage channel absolute input voltage range 4 18 v input voltage range 0 to 28.8 v vbat input current vbat = 18v 3 5.5 8 a temperature channel v ref = (reg_avdd, gnd_sw) / 2 absolute input voltage range 100 1300 mv input voltage range 0 to v ref v vtemp input current 1 2.5 100 na voltage reference adc precision reference internal v ref 1.2 v power up time 1 0.5 ms initial accuracy 1 measured at t a = 25c ?0.15 0.15 % temperature coefficient 1, 24 ?20 5 +20 ppm/c reference long-term stability 25 100 ppm/1000 hr external reference input range 26 0.1 1.3 v v ref divide by 2 initial error 1 0.1 0.3 %
aduc7030/aduc7033 preliminary technical data rev. pre | page 8 of 150 parameter test conditions/comments min typ max unit adc low power reference internal v ref 1.2 v initial accuracy measured at t a = 25c ?5 5 % initial accuracy 11 using adcref. measured at t a = 25c 0.1 % temperature coefficient 1, 24 ?300 150 +300 ppm/c resistive attenuator divider ratio 24 resistor mismatch drift 3 ppm/c adc ground switch resistance direct path to ground 10 ? 20 k? resistor selected 10 20 30 k ? input current 6 ma temperature sensor 27 after user calibration accuracy mcu in power down or standby mode 3 c mcu in power down or standby mode, temperature range = ?25c to +65c 2 c power-on reset (por) por trip level refers to voltage at vdd pin 2.85 3.0 3.15 v por hysteresis 300 mv reset time-out from por 20 ms low voltage flag (lvf) lvf level refers to voltage at vdd pin 1.9 2.1 2.3 v power supply monitor (psm) psm trip level refers to voltage at vdd pin 6.0 v watchdog timer ( wdt ) timeout period 1 32.768 khz clock, 256 pre-scale 0.008 512 sec timeout step size 7.8 ms flash/ee memory 1 endurance 28 10,000 cycles data retention 29 t j = 85c 20 years digital inputs all digital inputs except ntrst input leakage current input (high) = reg_dvdd 1 10 a input pull-up current input (low) = 0v 10 20 80 a input capacitance 10 pf input leakage current ntrst only: input (low) = 0 v 1 10 a input pull-down current ntrst only: input (high) = reg_dvdd 30 55 100 a logic inputs 1 all logic inputs vinl, input low voltage 0.4 v vinh, input high voltage 2.0 v crystal oscillator 1 logic inputs, xtal1 only vinl, input low voltage 0.8 v vinh, input high voltage 1.7 v xtal1 capacitance 12 pf xtal2 capacitance 12 pf
preliminary technical data aduc7030/aduc7033 rev. pre | page 9 of 150 parameter test conditions/comments min typ max unit on-chip oscillators low power oscillator 131.072 khz accuracy 30 includes drift data from 1000 hr life-test ?6 3 % precision oscillator 131.072 khz accuracy includes drift data from 1000 hr life-test -1.2 1.2 % mcu clock rate 8 programmable core clock selections within this range (binary divisions 1, 2, 4, 8..64, 128) 0.160 10.24 20.48 mhz mcu start-up time at power-on includes kernel power-on execution time 25 ms after reset event includes kernel power-on execution time 5 ms from mcu power-down oscillator running wakeup from interrupt 2 ms wakeup from lin 2 ms crystal powered down wakeup from interrupt 500 ms internal pll lock time 1 ms lin i/o general baud rate 1000 20,000 bits/sec vdd supply voltage range for which the lin interface is functional 7 18 v input capacitance 5.5 pf lin comparator response time 1 using 22ohm resistor 38 90 s i lin dom max current limit for driver when lin bus is in dominant state. v bat = v bat (max) 40 200 ma i lin_pas_rec driver off ; 7.0 v < v bus < 18 v; v dd = v lin ?0.7 v 20 a i lin_pas_dom 1 input leakage vlin = 0 v ?1 ma i lin_no_gnd 31 control unit disconnected from ground gnd = v dd ; 0 v v lin < 18 v ; v bat = 12 v ?1 +1 ma v lin_dom 1 lin receiver dominant state, v dd > 7.0 v 0.4 v dd v v lin_rec 1 lin receiver recessive state, v dd > 7.0 v 0.6 v dd v v lin_cnt 1 lin receiver centre voltage, v dd > 7.0 v 0.475 v dd 0.5 v dd 0.525 v dd v v hys 1 lin receiver hysteresis voltage 0.175 v dd v v lin_dom_drv_losup 1 lin dominant output voltage, v dd 7 v, r l 500 ? 1.2 v v lin_dom_drv_hisup lin dominant output voltage, v dd 18 v, r l 500 ? 2 v v lin_dom_drv_losup 1 lin dominant output voltage, vdd 7v, r l 1000 ? 0.6 v v lin_dom_drv_hisup 1 lin dominant output voltage, vdd 18 v, r l 1000 ? 0.8 v v lin_recessive lin recessive output voltage 0.8 v dd v v bat -shift 31 0 0.1 v dd v gnd-shift 31 0 0.1 v dd v r slave slave termination resistance 20 30 47 k ? v serial diode 31 voltage drop at the serial diode d ser_int 0.4 0.7 1 v lin i/o general contd bus load conditions (cbus||rbu ): 1nf||1k ?; 6.8nf|| 660 ? ; 10nf || 500 ? symmetry of transmit propagation delay 1 vdd min = 7 v ?2 +2 s receive propagation delay 1 vdd min = 7 v 6 s symmetry of receive propagation delay 1 vdd min = 7 v ?2 +2 s
aduc7030/aduc7033 preliminary technical data rev. pre | page 10 of 150 parameter test conditions/comments min typ max unit lin v2.0 specification bus load conditions (cbus||rbus): 1 nf||1 k ? ; 6.8 nf|| 660 ? ; 10 nf||500 ? d1 duty cycle 1 th rec(max) = 0.744 v bat th dom(max) = 0.581 v bat v sup = 7.0 v18 v; t bit = 50 s d1 = t bus_rec(min) /(2 t bit ) 0.396 d2 duty cycle 2 th rec(min) = 0..284 v bat th dom(min) = 0.422 v bat v sup = 7.0 v18 v; t bit = 50 s d2 = t bus_rec(max) /(2 t bit ) 0.581 bsd i/o 32 baud rate 1164 1200 1236 bits/sec vol, output lo-voltage 1.2 v voh, output hi-voltage 0.8 v dd v dd v ilh, high leakage current v bsd = v dd or 0 v ?5 5 20 ua i o(sc) short-circuit output current v bsd = v dd = 12 v 50 80 120 ma vinl, input low voltage 1.8 v vinh, input high voltage 0.7 v dd v wake r l = 1 k?, c bus = 91 nf, r limit = 39 ? vdd 1 supply voltage range for which the wake pin is functional 7 18 v v oh 33 output high level 5 v v ol 33 output low level 2 v v ih input high level 4.6 v v il input low level 1.2 v monoflop timeout timeout period 0.5 1.3 2 sec i o(sc) short-circuit output current 100 ma serial test interface r l = 500 ?, c bus = 2.4 nf, r limit = 39 ? baud rate 40 kbps vdd supply voltage range for wh ich sti is functional 7 18 v v oh output high level 0.6 v dd v ol output low level 0.4 v dd v ih input high level 0.6 v dd v il input low level 0.4 v dd package thermal specifications thermal shutdown 134 140 150 160 c thermal impedance ( ja ) 35 48 lfcsp, stacked die 45 c/w thermal impedance ( ja ) 35 48 lqfp, stacked die 75 c/w power requirements power supply voltages vdd (battery supply) 3.5 18 v reg_dvdd, reg_avdd 36 2.5 2.6 2.7 v power consumption idd C mcu normal mode 37 mcu clock rate = 10.24mhz, adc off 10 20 ma idd C mcu normal mode 37 mcu clock rate = 20.48mhz, adc off 20 ma idd C mcu powered down 1 adc low power mode, measured over an ambient temperature range of ?10c to +40c (continuous adc conversion ) 300 400 a
preliminary technical data aduc7030/aduc7033 rev. pre | page 11 of 150 parameter test conditions/comments min typ max unit iddCmcu powered down 1 adc low power mode, measured over an ambient temperature range of ?40c to +85c (continuous adc conversion ) 300 500 a idd C mcu powered down 1 adc low power-plus mode, measured over an ambient temperature range of ?10c to +40c (continuous adc conversion ) 520 700 a idd C mcu powered down average current, measured with wake and watchdog timer clocked from low power oscillator (?40c to +85c) 120 300 a idd C mcu powered down 1 average current, measured with wake and watchdog timer clocked from low power oscillator over an ambient temperature range of ?10c to +40c 120 175 a idd Ccurrent adc 1.7 ma idd Cvoltage/temperature adc 0.5 ma idd C precision oscillator 400 a 1 these numbers are not production tested, but are guaranteed by design and/or characterization data at production release. 2 valid for current adc gain setting of pga = 4 to 64. 3 these numbers include temperature drift. 4 tested at gain range = 4; self-offset calibration removes this error. 5 measured with an internal short af ter an initial offset calibration. 6 measured with an internal short 7 these numbers include internal reference temperature drift. 8 factory calibrated at gain = 1. 9 system calibration at specific gain rang e will remove the error at this gain range 10 includes an initial system calibration 11 when used in conjunction with adcref, the low power mode reference error mmr. 12 using adc normal mode voltage reference 13 typical noise in low power modes is measured with chop enabled. 14 voltage channel specifications incl ude resistive attenuator input stage 15 system calibration will remove this error 16 rms noise is referred to voltage attenuator input, for example at f adc =1khz, typical rms noise at the adc input is 7.5uv, scaled by the attenuator (24) yields these input referred noise figures 17 adc self offset calibration will remove this error. 18 valid after an initial self calibration 19 system calibration will remove this error 20 in adc low power mode the input range is fixed at 9.375mv. in adc lo w power plus mode the input range is fixed at 2.34375mv. 21 it is possible to extend the adc input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. this approach can also be used to reduce the adc input range (lsb size). 22 limited by minimum absolute input voltage range. 23 valid for a differential input less than 10mv 24 measured using box method 25 the long-term stability specification is non cumulative. the drift in subsequent 1,000 hour periods is si gnificantly lower tha n in the first 1,000 hour period. 26 references of up to reg_av dd can be accommodated by enab ling an internal divide-by-2 27 die temperature. 28 endurance is qualified to 10,000 cycles as per jedec std. 22 method a117 and measured at -40c, +25c and +125c. typical endu rance at 25c is 170,000 cycles. 29 retention lifetime equivalent at junction temperature (tj) = 85c as per jedec std. 22 method a117. retenti on lifetime will de -rate with junction temperature. 30 low power oscillator can be ca librated against either the precis ion oscillator or the external 32.768khz crystal in user code 31 these numbers are not production tested, bu t are supported by lin compliance testing. 32 bsd electrical specifications, except high and low voltage levels, are per lin2.0 with pull-up resistor disabled and c load = 10nf max. 33 specified after rlimit of 39ohms 34 the mcu core is not shutdown but interrupte d and high voltage i/o pins are disabled in response to a thermal shutdown event. 35 thermal impedance can be used to calculate the thermal gradient from ambient to die temperature. 36 internal regulated supply available at reg_dvdd (i source =5ma), and reg_avdd (i source =1ma) 37 typical, additional supply current consum ed during flash memory program and eras e cycles is 7ma and 5ma respectively.
aduc7030/aduc7033 preliminary technical data rev. pre | page 12 of 150 timing specifications spi timing specifications table 2 spi master mode timing (phase mode 1) parameter description min typ max unit t sl sclock low pulse width (spidiv + 1) t hclk ns t sh sclock high pulse width (spidiv + 1) t hclk ns t dav data output valid after sclock edge ns t dsu data input setup time before sclock edge ns t dhd data input hold time0 after sclock edge ns t df data output fall time ns t dr data output rise time ns t sr sclock rise time ns t sf sclock fall time ns sclock (polarity = 0) sclock (polarity = 1) mosi miso msb in bits 6 ? 1 lsb in lsb bits 6 ? 1 msb t sh t sl t sr t dav t df t dr t dsu t dhd t sf 05994-002 figure 2. spi master mode timing (phase mode = 1)
preliminary technical data aduc7030/aduc7033 rev. pre | page 13 of 150 table 3. spi master mode timing (phase mode = 0) parameter description min typ max unit t sl sclock low pulse width (spidiv + 1) t hclk ns t sh sclock high pulse width (spidiv + 1) t hclk ns t dav data output valid after sclock edge ns t dosu data output setup before sclock edge ns t dsu data input setup time before sclock edge ns t dhd data input hold time after sclock edge ns t df data output fall time ns t dr data output rise time ns t sr sclock rise time ns t sf sclock fall time ns sclock (polarity = 0) sclock (polarity = 1) t sh t sl t sr t sf miso msb in bits 6 ? 1 lsb in t dsu t dhd mosi lsb bits 6 ? 1 msb t dav t df t dr t dosu 0 5994-003 figure 3. spi master mode timing (phase mode = 0)
aduc7030/aduc7033 preliminary technical data rev. pre | page 14 of 150 table 4. spi slave mode timing (phase mode = 1) parameter description min typ max unit t cs cs to sclock edge ns t sl sclock low pulse width (spidiv + 1) t hclk ns t sh sclock high pulse width (spidiv + 1) t hclk ns t dav data output valid after sclock edge ns t dsu data input setup time before sclock edge ns t dhd data input hold time after sclock edge ns t df data output fall time ns t dr data output rise time ns t sr sclock rise time ns t sf sclock fall time ns t sfs cs high after sclock edge ns 05994-004 mosi msb in bits 6 ? 1 lsb in t dsu t dhd sclock (polarity = 0) cs sclock (polarity = 1) t sh t cs t sl t sr t sf t dav miso lsb bits 6 ? 1 msb t df t dr t sfs figure 4. spi slave mode timing (phase mode = 1)
preliminary technical data aduc7030/aduc7033 rev. pre | page 15 of 150 table 5. spi slave mode timing (phase mode = 0) parameter description min typ max unit t cs cs to sclock edge ns t sl sclock low pulse width (spidiv + 1) t hclk ns t sh sclock high pulse width (spidiv + 1) t hclk ns t dav data output valid after sclock edge ns t dsu data input setup time before sclock edge ns t dhd data input hold time after sclock edge ns t df data output fall time ns t dr data output rise time ns t sr sclock rise time ns t sf sclock fall time ns t docs data output valid after cs edge ns t sfs cs high after sclock edge ns 05994-005 sclock (polarity = 0) cs sclock (polarity = 1) t sh t cs t sl t sr t sf t sfs mosi msb in bits 6 ? 1 lsb in t dsu t dhd t dav miso lsb bits 6 ? 1 msb t df t dr t docs figure 5. spi slave mode timing (phase mode = 0)
aduc7030/aduc7033 preliminary technical data rev. pre | page 16 of 150 lin timing specifications 05994-005 transmit input to transmitting node v sup (transceiver supply of transmitting node) rxd (output of receiving node 1) rxd (output of receiving node 2) recessive th rec (max) t lin_dom (max) t lin_rec (min) t lin_dom (min) t lin_rec (max) th dom (max) th rec (min) th dom (min) dominant thresholds of receiving node 1 lin bus thresholds of receiving node 2 t bit t bit t bit t rx_pdr t rx_pdr t rx_pdf t rx_pdf figure 6 : lin v2.0 timing specification
preliminary technical data aduc7030/aduc7033 rev. pre | page 17 of 150 terminology conversion rate the conversion rate specifies the rate at which an output result is available from the adc, once the adc has settled. the sigma-delta conversion techni ques used on this part mean that while the adc front-end signal is over-sampled at a relatively high sample rate, a subsequent digital filter is employed to decimate the output to give a valid 16-bit data conversion result at output rates from 1hz to 8 khz. it should also be noted that when software switches from one input to another (on the same adc), the digital filter must first be cleared and then allowed to average a new result. depending on the configuration of the adc and the type of filter this can take multiple conversion cycles. integral non linearity (inl) this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are zero scale, a point 0.5 lsb below the first code transition and full scale, a point 0.5 lsb above the last code transiti on (111 . . . 110 to 111 . . . 111). the error is expressed as a percentage of full scale. no missing codes this is a measure of the differential non-linearity of the adc. the error is expressed in bits and specifies the number of codes (adc results) as 2^n bits, where is n = no missing codes, guaranteed to occur through the full adc input range. offset error this is the deviation of the first code transition adc input voltage from the ideal first code transition. offset error drift offset error drift is the variation in absolute offset error with respect to temperature. this error is expressed as lsbs per c. gain error this is a measure of the span error of the adc. it is a measure of the difference between the measured and the ideal span between any two points in the transfer function. output noise the output noise is specified as the standard deviation (or 1 x sigma) of adc output codes distribution collected when the adc input voltage is at a dc voltage. it is expressed as rms. the output or rms noise can be used to calculate the effective resolution of the adc as defined by the following equation effective resolution = log 2 (full-scale range/rms noise) bits the peak-to-peak noise is defined as the deviation of codes that fall within 6.6 sigma of the distribution of adc output codes collected when the adc input voltage is at dc. the peak-to- peak noise is therefore calculated as 6.6 times the rms noise. the peak-to-peak noise can be used to calculate the adc (noise free, code) resolution for which there will be no code flicker within a 6.6-sigma limit as defined by the following equation noise free code resolution = log 2 (full-scale range/peak-to- peak noise) bits data sheet acronyms adc analog to digital converter arm advanced risc machine jtag joint test action group lin local interconnect network lsb least significant byte/bit lvf low voltage flag mcu microcontroller mmr memory mapped register msb most significant byte/bit pid protected identifier por power on reset psm power supply monitor rms root mean square sti serial test interface
aduc7030/aduc7033 preliminary technical data rev. pre | page 18 of 150 absolute maximum ratings t a = ?40c to 115c unless otherwise noted table 6. parameter rating agnd to dgnd to vss to io_vss ?0.3 v to +0.3 v vbat to agnd ?22 v to +40 v v dd to vss ?0.3 v to +33 v v dd to vss for 1 second ?0.3 v to +40 v lin to io_vss ?16 v to +40 v sti/wu to io_vss ?3 v to +33 v wake continuous current 50 ma hv io pins short-circuit current 100 ma digital i/o voltage to dgnd ?0.3 v to reg_dv dd + 0.3 v v ref to agnd ?0.3 v to reg_av dd + 0.3 v adc inputs to agnd ?0.3 v to reg_av dd +0.3 v esd (hbm) rating lin, sti, wu and vbat 4 kv all other pins 2 kv storage temperature 125c junction temperature transient 150c continuous 130c lead temperature, soldering 260c reflow (15 sec) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data aduc7030/aduc7033 rev. pre | page 19 of 150 pin configuration and fu nction descriptions nc = no connect aduc7030/ aduc7033 top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 reset gpio_5/irq1/rxd gpio_6/txd gpio_7/irq4 gpio_8/irq5 tck tdi dgnd nc tdo ntrst tms 13 14 15 16 17 18 19 20 21 22 23 24 vbat vref gnd_sw nc nc vtemp iin+ iin? agnd agnd nc reg_avdd 48 47 46 45 44 43 42 41 40 39 38 37 lin/bsd io_vss sti nc vss nc vdd wu nc nc nc xtal2 36 35 34 33 32 31 30 29 28 27 26 25 xtal1 dgnd dgnd reg_dvdd nc gpio_4/eclk gpio_3/mosi gpio_2/miso gpio_1/sclk gpio_0/irq0/s s nc nc 05994-007 figure 7. pin configuration table 7. pin function descriptions pin no. mnemonic type 1 function 1 reset i reset input pin, active low. this pin has an inte rnal, weak pull-up resistor to reg_dvdd. if this pin is not being used, it can be left not conne cted. for added security and robustness, it is recommended that this pin be strapped via a resistor to reg_dvdd. 2 gpio_5/irq1/rxd i/o general purpose digital input/output 5, external in terrupt request 1, or receive data. this is a multifunction pin. by default and after power-on-r eset, this pin configures as an input. the pin has an internal weak pull-up resistor and when not in use, it can be left unconnected. this multifunction pin can be configured in one of three states, namely: general purpose digital i/o 5 external interrupt request 1, active high receive data for uart serial port 3 gpio_6/txd i/o general purpose digital input/output 6, transmit data. this is a multifunction pin. by default and after power-on-reset, this pin configures as an input. the pin has an internal weak pull-up resistor and when not in use, it can be left unconnected. this multifunction pin can be configured in one of two states, namely: general purpose digital i/o 6 transmit data for uart serial port 4 gpio_7/irq4 i/o general purpose digital input/output 7, external in terrupt request. this is a multifunction pin. by default and after power-on-reset, this pin conf igures as an input. the pin has an internal weak pull-up resistor and when not in use, it can be left unconnected. this multifunction pin can be configured in one of two states, namely: general purpose digital i/o 7 external interrupt request 4, active high 5 gpio_8/ irq5 i/o general purpose digital input/output 8, external in terrupt request. this is a multifunction pin. by default and after power-on-reset, this pin conf igures as an input. the pin has an internal weak pull-up resistor and when not in use, it can be left unconnected. this multifunction pin can be configured in one of two states, namely: general purpose digital i/o 8 external interrupt request 5, active high 6 tck i jtag test clock. this clock input pin is one of the standard 5-pin jtag debug ports on the part. tck is an input pin only and has an internal weak pull-up resistor. this pin can be left unconnected when not in use.
aduc7030/aduc7033 preliminary technical data rev. pre | page 20 of 150 pin no. mnemonic type 1 function 7 tdi i jtag test data input. this data input pin is on e of the standard 5-pin jtag debug ports on the part. tdi is an input pin only and has an internal weak pull-up resistor. this pin can be left unconnected when not in use. 8, 34, 35 dgnd s ground reference for on-chip digital circuits. 9, 16, 17, 23, 25, 26, 32, 38 to 40, 43, 45 nc no connect. these pins are not internally conne cted, but are reserved for possible future use. therefore, do not externally connect these pins. these pins can be grounded, if required. 10 tdo o jtag test data output. this da ta output pin is one of the standard 5-pin jtag debug ports on the part. tdo is an output pin only. on power-on, this output is disabled and pulled high via an internal weak pull-up resistor. this pin can be left unconnected when not in use. 11 ntrst i jtag test reset. this reset input pin is one of the standard 5-pin jtag debug ports on the part. ntrst is an input pin only and has an internal weak pull-down resistor. this pin can be left unconnected when not in use. nt rst is also monitored by the on-chip kernel to enable lin boot-load mode. 12 tms i jtag test mode select. this mode select input pin is one of the standard 5-pin jtag debug ports on the part. tms is an input pin only and has an internal weak pull-up resistor. this pin can be left unconnected when not in use. 13 vbat i battery voltage input to resistor divider. 14 vref i external reference input terminal. when this inp ut is not used, connect it directly to the agnd system ground. 15 gnd_sw i switch to internal analog ground reference. th is pin is the negative input for the external temperature channel and external reference. when this input is not used, connect it directly to the agnd system ground. 18 vtemp i external pin for ntc/ptc temperature measurement. 19 iin+ i positive differential input for current channel. 20 iin? i negative differential input for current channel. 21, 22 agnd s ground reference for on-chip precision analog circuits. 24 reg_avdd s nominal 2.6 v output from on-chip regulator. 27 gpio_0/irq0/ss i/o general purpose digital input/output 0, external in terrupt request 0, or spi interface. this is a multi-function pin. by default and after power-on-r eset, this pin is configured as an input. the pin has an internal weak pull-up resistor and if not being used it can be left unconnected. this multifunction pin can be configured in one of three states, namely: general purpose digital i/o 0 external interrupt request 0, active high spi interface, slave select input 28 gpio_1/sclk i/o general purpose digital input/output 1, spi interfac e. this is a multi-function pin. by default and after power-on-reset, this pin is configured as an input. the pin has an internal weak pull- up resistor and if not being used it can be le ft unconnected. this multi-function pin can be configured in one of 2 states, namely: general purpose digital i/o 1 spi interface, serial clock input 29 gpio_2/mis0 i/o general purpose digital input/output 2 is a mult i-function pin. by default and after power-on- reset, this pin is configured as an input. the pi n has an internal weak pull-up resistor and if not being used it can be left unconnected. this multi-function pin can be configured in one of 2 states, namely: general purpose digital i/o 2 spi interface, master input/slave output pin 30 gpio_3/mosi i/o general purpose digital input/output 3 is a multi- function pin. by default and after power-on- reset, this pin is configured as an input. the pi n has an internal weak pull-up resistor and if not being used it can be left unconnected. this multi-function pin can be configured in one of 2 states, namely: general purpose digital i/o 3 spi interface, master output/slave input pin
preliminary technical data aduc7030/aduc7033 rev. pre | page 21 of 150 pin no. mnemonic type 1 function 31 gpio_4/eclk i/o general purpose digital input/output 4 is a multi- function pin. by default and after power-on- reset, this pin is configured as an input. the pi n has an internal weak pull-up resistor and if not being used it can be left unconnected. this multi-function pin can be configured in one of 2 states, namely: general purpose digital i/o 4 output a 2.56mhz clock 33 reg_dvdd s nominal 2.6v output from the on-chip regulator 36 xtal1 o crystal oscillator output. if an external crys tal is not being used, this pin can be left unconnected. 37 xtal2 i crystal oscillator input. if an external crystal is not being used, this pin should be connected to the dgnd system ground. 41 wu i/o high voltage wake-up pin. this high voltage i/o pin has an internal 10 k? pull-down resistor and a high-side driver to vdd. if this pin is not being used, it should not be connected externally. 42 vdd s battery power supply to on-chip regulator 44 vss s ground reference for the internal voltage regulators 46 sti i/o serial test interface output pin. if this pin is not being used it should be connected externally to the io_vss ground reference 47 io_vss s ground reference for high voltage i/o pins 48 lin/bsd i/o lin serial interface input/output pin 1 i = input, o = output, s = supply
aduc7030/aduc7033 preliminary technical data rev. pre | page 22 of 150 theory of operation the aduc7030/aduc7033 are each a complete system solution for battery monitoring in 12 v automotive applica- tions. the device integrates all of the required features to precisely and intelligently monitor, process, and diagnose 12 v battery parameters including battery current, voltage, and temperature over a wide range of operating conditions. minimizing external system components, the device is powered directly from the 12 v battery. an on-chip, low drop-out regulator generates the supply voltage for three integrated 16-bit - adcs. the adcs precisely measure battery current, voltage, and temperature to characterize the car batterys state of health and charge. a flash/ee memory-based arm7? microcontroller (mcu) is also integrated on-chip and is used both to pre-process the acquired battery variables, and to manage communications from the aduc7030/aduc7033 to the main electronic control unit (ecu) via a local interconnect network (lin) interface that is integrated on-chip. both the mcu and the adc subsystem can be individually configured to operate in normal or flexible power saving modes of operation. in its normal operating mode, the mcu is clocked indirectly from an on-chip oscillator via the phase locked loop (pll) at a maximum clock rate of 20.48 mhz. in its power saving operating modes, the mcu can be totally powered down, waking up only in response to an adc conversion result ready, digital comparators, the wake-up timer, a por, or an external serial communication event. the adc can be configured to operate in a normal (full power) mode of operation, interrupting the mcu after various sample conversion events. the current channel features two low power modes, low power and low power plus, generating conversion results to a lower performance specification. on-chip factory firmware supports in-circuit flash/ee reprogramming via the lin or jtag serial interface ports, and nonintrusive emulation is also supported via the jtag interface. these features are incorporated into a low-cost quickstart? development system supporting the aduc7030/aduc7033. the aduc7030/aduc7033 operate directly from the 12 v battery supply and are fully specified over a temperature range of ?40c to +115c. the aduc7030/aduc7033 are functional, but with degraded performance, at temperatures from 115c to 125c. overview of the arm7tdmi core the arm7 core is a 32-bit reduced instruction set computer (risc), developed by arm ltd. the arm7tdmi is a von neumann-based architecture, meaning that it uses a single 32-bit bus for instruction and data. the length of the data can be 8, 16 or 32 bits and the length of the instruction word is either 16 bits or 32 bits, depending on the mode in which the core is operating. the arm7tdmi is an arm7 core with four additional features as listed in table 8. table 8. arm7tdmi feature description t support for the thumb (16-bit) instruction set d support for debug m enhanced multiplier i includes the embeddedice module to support embedded system debugging thumb mode (t) an arm instruction is 32 bits long. the arm7tdmi processor supports a second instruction set compressed into 16 bits, the thumb instruction set. faster code execution from 16-bit memory and greater code density can be achieved by using the thumb instruction set, which makes the arm7tdmi core particularly suited for embedded applications. however, the thumb mode has three limitations: ? relative to arm, the thumb code usually requires more instructions to perform that same task. therefore, arm code is best for maximizing the performance of time- critical code in most applications. ? the thumb instruction set does not include some instructions that are needed for exception handling, so arm code can be required for exception handling. ? when an interrupt occurs, the core vectors to the interrupt location in memory and executes the code present at this address. the first command is required to be in arm code. multiplier (m) the arm7tdmi instruction set includes an enhanced multiplier, with four extra instructions to perform 32-bit by 32-bit multiplication with 64-bit result, and 32-bit by 32-bit multiplication-accumulation (mac) with 64-bit result. embeddedice (i) the embeddedice module provides integrated on-chip debug support for the arm7tdmi. the embeddedice module contains the breakpoint and watchpoint registers that allow nonintrusive user code debugging. these registers are controlled through the jtag test port. when a breakpoint or watchpoint is encountered, the processor halts and enters debug state. once in a debug state, the processor registers can be interrogated, as well as the flash/ee, the sram, and the memory mapped registers.
preliminary technical data aduc7030/aduc7033 rev. pre | page 23 of 150 arm7 exceptions the arm7 supports five types of exceptions, with a privileged processing mode associated with each type. the five types of exceptions are ? normal interrupt or irq. it is provided to service general- purpose interrupt handling of internal and external events. ? fast interrupt or fiq. it is provided to service data transfer or communication channel with low latency. fiq has priority over irq. ? memory abort (prefetch and data). ? attempted execution of an undefined instruction. ? software interrupt (swi) instruction that can be used to make a call to an operating system. typically, the programmer defines interrupts as irq, but for higher priority interrupts, the programmer can define interrupts as of type fiq. the priority of these exceptions and vector address are listed in table 9. table 9. priority exception address 1 hardware reset 0x00 2 memory abort (data) 0x10 3 fiq 0x1c 4 irq 0x18 5 memory abort (prefetch) 0x0c 6 software interrupt 1 0x08 6 undefined instruction 1 0x04 1 a software interrupt and an undefined instruction exception have the same priority and are mutually exclusive. the list of exceptions in table 9.are located from 0x00 to 0x1c, with a reserved location at 0x14. this location is required to be written with either 0x27011970 or the checksum of page zero, excluding location 0x14. if this is not done, user code does not execute and lin download mode is entered. for more information, refer to the relevant lin download technote. arm registers the arm7tdmi has 16 standard registers. r0-r12 are used for data manipulation, r13 is the stack pointer, r14 is the link register and r15 is the program counter which indicates the instruction currently being executed. the link register contains the address from which the user has branched, if the branch and link command was used, or the command during which an exception occurred. the stack pointer contains the current location of the stack. as a general rule of thumb on an arm7tdmi, the stack starts at the top of the available ram area, and descends, using the area as required. a separate stack is defined for each of the exceptions. the size of each stack is user configurable and is dependent on the target application. on the aduc7030/ aduc7033 the stack begins at 0x00040ffc and descends. when programming using high level languages, such as c, it can be possible to ensure that the stack does not overflow. this is dependent on the compiler used. when an exception occurs, some of the standard register are replaced with registers specific to the exception mode. all exception modes have replacement banked registers for the stack pointer (r13) and the link re gister (r14) as represented in figure 2. the fiq mode has more registers (r8 to r12) supporting faster interrupt processing. with the increased number of non-critical registers, the interrupt may be processed without the need to save or restore these registers, which reduces the response time of the interrupt handling process. more information relative to the programmers model and the arm7tdmi core architecture can be found in the following documents available from arm ltd.: ddi0029g, arm7tdmi technical reference manual. ddi0100e, arm architecture reference manual . 05994-008 usable in user mode system modes only spsr_und spsr_irq spsr_abt spsr_svc r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r13_und r14_und r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (pc) r13_irq r14_irq r13_abt r14_abt r13_svc r14_svc spsr_fiq cpsr user mode fiq mode svc mode abort mode irq mode undefined mode figure 8. aduc7030/aduc7033 register organization interrupt latency the worst case latency for an fiq consists of the longest time the request can take to pass through the synchronizer, plus the time for the longest instruction to complete (the longest instruction is an ldm) which loads all the registers including the pc, plus the time for the data abort entry, plus the time for fiq entry. at the end of this time, the arm7tdmi will be executing the instruction at 0x1c (fiq interrupt vector address). the maximum total time is 50 processor cycles, which is just over 2.44 s in a system using a continuous 20.48 mhz processor clock. the maximum irq latency calculation is similar, but must allow for the fact that fiq has higher priority and could delay entry into the irq handling routine for an arbitrary length of time. this time may be reduced to 42 cycles if the ldm command is not used, some compilers have an option to compile without using this command. another option is to run the part in thumb mode where this is reduced to 22 cycles.
aduc7030/aduc7033 preliminary technical data rev. pre | page 24 of 150 the minimum latency for fiq or irq interrupts is five cycles. this consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. note that the arm7tdmi will initially (1 st instruction) run in arm (32-bit) mode when an exception occurs. the user may immediately switch from arm mode to thumb mode if required, e.g. when executing interrupt service routines. memory organisation the arm7, a von neumann architecture, mcu core sees memory as a linear array of 2 32 byte locations. as shown in figure 10 and figure 11, the aduc7030 and the aduc7033 both map this into 4 distinct user areas namely, a re-mappable memory area, an sram area, a flash/ee area and a memory mapped register (mmr) area. 1. for the aduc7030,the first 30kbytes of this memory space is used as an area into which the on-chip flash/ee or sram can be remapped. for the aduc7033, the first 94kbytes of this memory space is used as an area into which the on-chip flash/ee or sram can be remapped. 2. both the aduc7030 and the aduc7033, feature a second 4kbyte area at the top of the memory map used to locate the memory mapped registers (mmr), through which all on-chip peripherals are configured and monitored. 3. the aduc7030 features a sram size of 4 kbyte the aduc7033 features a sram size of 6 kbyte 4. the aduc7030 features 32 kbyte of on-chip flash/ee memory. 30kbyte of on-chip flash/ee memory are available to the user. the aduc7033 features 96 kbyte of on-chip flash/ee memory. 94kbyte of on-chip flash/ee memory are available to the user for both the aduc7030 and aduc7033, 2 kbytes are reserved for the on-chip kernel. any access, either reading or writing, to an area not defined in the memory map will result in a data abort exception. memory format the aduc7030/aduc7033 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address. 0 5994-009 bit 31 byte 2 a 6 2 . . . byte 3 b 7 3 . . . byte 1 9 5 1 . . . byte 0 8 4 0 . . . bit 0 32 bits 0xffffffffh 0x00000004h 0x00000000h figure 9. little endian format 0 5994-010 00040fffh 00040000h ffff0fffh ffff0000h mmrs 00087fffh 00080000h flash/ee sram 00007fffh 00000000h re-mappable memory space (flash/ee or sram) reserved reserved reserved reserved figure 10. aduc7030 memory map 0 5994-011 00417ffh 00040000h ffff0fffh ffff0000h mmrs 00097fffh 00080000h flash/ee sram 0017fffh 00000000h re-mappable memory space (flash/ee or sram) reserved reserved reserved reserved figure 11. aduc7033 memory map sram the aduc7030 features 4kbytes of sram, organized as 1024 x 32 bits, i.e. 1024 words, which is located at 0x40000. the aduc7033 features 6kbytes of sram, organized as 1536 x 32 bits, i.e. 1536 words, which is located at 0x40000. the ram space can be used as data memory and also as a volatile program space. arm code can run directly from sram at full clock speed given that the sram array is configured as a 32-bit wide memory array. sram is read/writeable in 8-, 16-, 32-bit segments. remap the arm exception vectors are all situated at the bottom of the memory array, from address 0x00000000 to address 0x00000020.
preliminary technical data aduc7030/aduc7033 rev. pre | page 25 of 150 by default, after a reset, the flash/ee memory is logically mapped to address 0x00000000. it is possible to logically remap the sram to address 0x00000000. this is done by a setting bit zero of the sysmap0 mmr, which is located at 0xffff0220. to revert flash/ee to 0x00000000, bit zero of sysmap0 is cleared. it may be desirable to remap ram to 0x00000000 to optimize the interrupt latency of the aduc7030/aduc7033, as code may be run in full 32-bit arm mode and at the maximum core speed. it should be noted that when an exception occurs, the core will default to arm mode. remap operation when a reset occurs on the aduc7030/aduc7033, execution starts automatically in the factory programmed internal configuration code. this so called kernel is hidden and cannot be accessed by user code. if the aduc7030/aduc7033 is in normal mode, it will execute the power-on configuration routine of the kernel and then jump to the reset vector address, 0x00000000, to execute the users reset exception routine. since the flash/ee is mirrored at the bottom of the memory array at reset, the reset routine must always be written in flash/ee. the remap command must be executed from the absolute flash/ee address, and not from the mirrored, remapped segment of memory, as this may be replaced by sram. if a remap operation is executed whilst operating code from the mirrored location, prefetch/data aborts may occur or the user may observe abnormal program operation. any kind of reset will logically remap the flash/ee memory to the bottom of the memory array. sysmap0 register: name: sysmap0 address: 0xffff0220 default value: updated by the kernel access: read/write access function: this 8-bit register allows user code to remap either ram or flash/ee space into the bottom of the arm memory space starting at location 0x00000000. table 10. sysmap0 mmr bit designations bit description 7 to 1 reserved these bits are reserved and should be written as 0 by user code 0 remap bit. set by the user to remap the sram to 0x00000000. cleared automatically after reset to remap the flash/ee memory to 0x00000000.
aduc7030/aduc7033 preliminary technical data rev. pre | page 26 of 150 aduc7030/aduc7033 reset there are four kinds of reset: external reset, power-on-reset, watchdog reset and software reset. the rststa register indicates the source of the last reset and can also be written by user code to initiate a software reset event. the bits in this register can be cle ared to 0 by writing to the rstclr mmr at 0xffff0234. the bit designations in rstclr mirror those of rststa. these registers can be used during a reset exception service routine to identify the source of the reset. the implications of all four kinds of reset event are tabulated in table 11 below. table 11. device r eset implications impact reset reset external pins to default state kernel executed reset all external mmrs(excluding rststa reset all hv indirect registers peripherals reset watchdog timer reset ram valid rststa (status after reset event) por note 1 rststa[0] =1 watchdog reset rststa[1] =1 software reset rststa[2] =1 external reset pin rststa[3] =1 note 1: if lvf is enabled(hvcfg0[2]), ram has not been corrupted by the por reset mechanism if lvf status bit hvsta[6] is 1. rststa register: name: rststa address: 0xffff0230 default va lu e: depends on type of reset access: read/write access function: this 8-bit register indicates the source of the last reset event and can also be written by user code to initiate a software reset. rstclr register: name: rstclr address: 0xffff0234 access: wr ite only function: this 8-bit write only register clears the corresponding bit in rststa. table 12. rststa/rstclr mmr bit designations bit description 7 to 4 not used these bits are not used and will always read as 0 3 external reset set to 1 automatically when an external reset occurs cleared by setting the corre sponding bit in rstclr 2 software reset set to 1 by user code to generate a software reset. cleared by setting the corre sponding bit in rstclr 1 watchdog timeout set to 1 automatically when a watchdog timeout occurs cleared by setting the corre sponding bit in rstclr 0 power-on-reset set automatically when a power-on-reset occurs cleared by setting the corre sponding bit in rstclr note: if the "software reset" bit in rststa is set, any write to rstclr that does not clear this bit will generate a software reset
preliminary technical data aduc7030/aduc7033 rev. pre | page 27 of 150 flash/ee memory and the aduc7030/aduc7033 the aduc7030/aduc7033 incorporate flash/ee memory technology on-chip to provide the user with nonvolatile, in- circuit reprogrammable memory space. like eeprom, flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. thus, flash memory is often and more correctly referred to as flash/ee memory. overall, flash/ee memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit program- mability, high density, and low cost. incorporated in the aduc7030/aduc7033, flash/ee memory technology allows the user to update program code space in-circuit, without the need to replace one time programmable (otp) devices at remote operating nodes. the flash/ee memory is physically located at 0x80000. upon a hard reset, it logically maps to 0x00000000. the factory default contents of all flash/ee memory locations is 0xff. flash/ee can be read in 8/16/32 bit segments, and written in segments of 16 bits. the flash/ee is rated for 10k endurance cycles. this rating is based on the number of times that each individual byte is cycled i.e. erased and programmed. a redundancy scheme may be implemented in software to ensure greater than 10k cycles endurance. the user can also write data va riables to the flash/ee memory during run-time code execution, for example, for storing diagnostic battery parameter data. the entire flash/ee is available to the user as code and non- volatile data memory. there is no distinction between data and program, as arm code shares the same space. the real width of the flash/ee memory is 16 bits, meaning that in arm mode (32-bit instruction), two accesses to the flash/ee are necessary for each instruction fetch. when operating at speeds less than 20.48 mhz the flash/ee memory controller can transparently fetch the second 16-bit half word (part of the 32-bit arm op- code) within a single core clock period. it is, therefore, recommended that for speeds less than 20.48 mhz, that is, cd > 0, that arm mode is used. for 20.48mhz operation, that is, cd = 0 , it is recommended to operate in thumb mode. the page size of this flash/ee memory is 512 bytes. typically, it takes the flash/ee controller 20 ms to erase a page, irrespective of cd. to write a 16-bit word at cd = 0, 1, 2, 3 requires 50 s; 70 s at cd=4, 5; 80 s at cd=6; and 105 s at cd=7. it is possible to write to a single 16 bit location only twice between erases, that is, it is possible to walk bytes, not bits. if a location is written to more than twice, then it is possible that the contents of the flash/ee page may be corrupted. the flash/ee memory can be programmed in-circuit, using a serial download mode via the lin interface or the integrated jtag port. (1) serial downloading (in-circuit programming) the aduc7030/aduc7033 facilitate code download via the lin pin. for more information please refer to the aduc7030/aduc7033 lin download protocol technote. (2) jtag access the aduc7030/aduc7033 feature an on-chip jtag debug port to facilitate code download and debug. aduc7030 flash/ee memory the total 32kbytes of flash/ee are organized as 15k x 16 bits. 30kbytes are user space and 2kbytes are reserved for boot loader/kernel space. aduc7033 flash/ee memory the total 96kbytes of flash/ee are organized as 47k x 16 bits. 94kbytes user space and 2kbytes reserved for boot loader/kernel space. aduc7030 flash/ee control interface the access to and control of the flash/ee memory on the aduc7030 is managed by an on-chip memory controller. the controller manages the flash/ee memory as single block of 32 kbytes. it should be noted that mcu core is halted until the command is completed. user software must ensure that the flash/ee controller has completed any erase or write cycle before the pll is powered down. if the pll is powered down before an erase or write cycle is completed, the flash/ee page can be corrupted. user code, lin and jtag programming use the flash/ee control interface, consists of the following mmrs: fee0sta: read only register, reflects the status of the flash/ee control interface fee0mod: sets the operating mode of the flash/ee control interface fee0con: 8-bit command register. the commands are interpreted as described in table 13. fee0dat: 16-bit data register. fee0adr: 16-bit address register. fee0sig: holds the 24-bit code signature as a result of the signature command being initiated.
aduc7030/aduc7033 preliminary technical data rev. pre | page 28 of 150 fee0hid: protection mmr. controls read and write protection of the flash/ee memory code space. if previously configured via the fee0pro register, fee0hid can require a software key to enable access. fee0pro: a buffer of the fee0hid register that stores the fee0hid value, so it is automatically downloaded to the fee0hid registers on subsequent reset and power-on events the following sections describe in detail the bit designations of each of flash/ee control mmrs. fee0con register: name: fee0con address: 0xffff0e08 default value: 0x07 access: read/write access function: this 8-bit register is written by user code to control the operating modes of the flash/ee memory controller. table 13. command codes in fee0con code command description 0x00 * reserved reserved, this command should not be written by user code 0x01 1 single read load fee0dat with the 16-bit data indexed by fee0adr 0x02 1 single write write fee0dat at the address pointed by fee0adr. this operation takes 50 s. 0x03 1 erase-write erase the page indexed by fee0adr and write fee0dat at the location pointed by fee0adr. this operation takes 20ms 0x04 1 single verify compare the contents of the location pointed by fee0adr to the data in fee0dat. the result of the comparison is returned in fee0sta bit 1 0x05 1 single erase erase the page indexed by fee0adr 0x06 1 mass erase erase 30kbytes of user space. the 2kbyte kernel is prot ected. this operation takes 1.2s to prevent accidental execution, a command sequence is required to exec ute this instruction, th is is described below. 0x07 idle default command. 0x08 reserved reserved, this command should not be written by user code 0x09 reserved reserved, this command should not be written by user code 0x0a reserved reserved, this command should not be written by user code 0x0b signature this command will result in a 24-bit lfsr based signature been generated and loaded into fee0sig. if fee0adr is less than 0x87800, this command will result in a 24-bit lfsr based signature of the user code space from the page specified in fee0adr upwards, in cluding the kernel, security bits and flash/ee key. if fee0adr is greater than 0x87800, the kernel and manu facturing data is signed. this operation takes 120us. 0x0c protect this command can be run only once. the value of fee0pr o is saved and can be removed only with a mass erase (0x06) or with the key 0x0d reserved reserved, this command should not be written by user code 0x0e reserved reserved, this command should not be written by user code 0x0f ping no operation, interrupt generated 1 the fee0con will always read 0x07 immediatel y after execution of any of these commands.
preliminary technical data aduc7030/aduc7033 rev. pre | page 29 of 150 command sequence for executing a mass erase giving the significance of the mass erase command, a specific code sequence must be executed to initiate this operation. 1. set bit 3 in fee0mod. 2. write 0xffc3 in fee0adr 3. write 0x3cff in fee0dat 4. run the mass erase command 0x06 in fee0con this sequence is illustrated in the following example: fee0mod= 0x08 fee0adr= 0xffc3 fee0dat= 0x3cff fee0con= 0x06; // mass-erase command while (fee0sta & 0x04){} //wait for command to finish fee0sta register: name: fee0sta address: 0xffff0e00 default value: 0x20 access: read only function: this 8-bit read only register can be read by user code and reflect the current status of the flash/ee memory controller. table 14. fee0sta mmr bit designation bit description 15 to 4 not used these bits are not used and will always read as 0. 3 flash/ee interrupt status bit set automatically when an interrupt occurs, i.e. when a command is complete and the flash/ee interrupt enable bit in the fee0mod register is set cleared automatically when the fee0sta register is read by user code 2 flash/ee controller busy set automatically when the flash/ee controller is busy cleared automatically when the controller is not busy 1 command fail set automatically when a command written to fee0concompletes unsuccessfully cleared automatically when the fee0sta register is read by user code 0 command successful set automatically by mcu when a command is completed successfully cleared automatically when the fee0sta register is read by user code
aduc7030/aduc7033 preliminary technical data rev. pre | page 30 of 150 fee0mod register: name: fee0mod address: 0xffff0e04 default value: 0x00 access: read/write access function: this register is written by user code to configure the mode of operation of the flash/ee memory controller. table 15. fee0mod mmr bit designation bit description 15 to 7 not used these bits are reserved for future functionalit y and should be written as 0 by user code 6, 5 flash/ee security lock bits these bits must be written as [6,5] = 1,0 to complete the flash/ee security protect sequence 4 flash/ee controller command complete interrupt enable this bit is set to 1 by user code to en able the flash/ee controller to generate an interrupt upon completion of a flash/ee command. this bit is cleared to disable the generation of a flas h/ee interrupt upon completion of a flash/ee command. 3 flash/ee erase/write enable set by user code to enable the flash/ee erase and write access via fee0con cleared by user code to disable the flash/ee erase and write access via fee0con 2 reserved 1 flash/ee controller abort enable this bit is set to 1 by user code to enable the flash/ee controller abort functionality. 0 reserved fee0adr registers: name: fee0adr address: 0xffff0e10 default value: non zero. please see the system identification section access: read/write access function: this 16-bit register dictates the address upon which any flash/ee command executed via fee0con acts upon. fee0dat registers : name: fee0dat address: 0xffff0e0c default value: 0x0000 access: read/write access function: this 16-bit register contains the data either read from or to be written to the flash/ee memory.
preliminary technical data aduc7030/aduc7033 rev. pre | page 31 of 150 aduc7030 flash/ee memory security the 30 kbyte of flash/ee memory available to the user can be read and write protected using the ffe0hid register. the fee0hid mmr protects the 30 kbytes. bits 0-28 of this register protect page 0 to page 57 from writing. each bit protects 2 pages, that is, 1 kbytes. bit 29 to bit 30 protect page 58 and page 59 respectively, that is, each bit write protects a single page of 512 bytes. the msb of this register (bit31) protects the entire flash/ee from been read through jtag. the fee0pro register mirrors the bit definitions of the fee0hid mmr. the fee0pro mmr allows user code to lock the protection or security configuration of the flash/ee memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. this flexibility allows the user to set and test protection settings temporarily using the fee0hid mmr and subsequently lock the required protection configuration (using fee0pro) when shipping protection systems into the field. flash/ee memory protection registers: name: fee0hid and fee0pro address: 0xffff0e20 (for fee0hid) and 0xffff0e1c (for fee0pro) default value: 0xffffffff (for fee0hid) and 0x00000000 (for fee0pro) access: read/write access function: these registers are written by user code to configure the protection of the flash/ee memory. table 16. fee0hid and fee0 pro mmr bit designations bit description 31 read protection cleared by user to read protect the 32-kbyte flash/ee block code. set by user to allow read access to the 32-kbyte flash/ee block via jtag. 30 write protection bit this bit is set by user code to unprotect protect page 59. this bit is cleared by user code write protect page 59. 29 write protection bit this bit is set by user code to unprotect page 58. this bit is cleared by user code write protect page 58. 28- 0 write protection bits when set by user code these bits unprotect page 0 to page 57 of the 30 kb flash/ee code memory. each bit write protects 2 pages and each pages consists of 512 bytes. when cleared by user code these bits will write protect pages 0-57 of the 30kb flash/ ee code memory. each bit write protects tw o pages and each page consists of 512 bytes.
aduc7030/aduc7033 preliminary technical data rev. pre | page 32 of 150 in summary, there are three levels of protection: 1. temporary protection can be set and removed by writing directly into fee0hid mmr. this register is volatile and therefore protection is only in place while the part remains powered on. this protection is not reloaded after a power cycle. 2. keyed permanent protection can be set via fee0pro to lock the protection configuration. the software key used at the start of the required fee0pro write sequence is saved once and must subsequently be used for any subsequent access of the fee0hid or fee0pro mmrs. a mass erase sets the key back to 0xffff but also erases the entire user code space. 3. permanent protection can be set via fee0pro, similarly to keyed permanent protection, the only difference been that the software key used is 0xdeaddead. once the fee0pro write sequence is saved, only a mass erase sets the key back to 0xffffffff. this also erases the entire user code space. sequence to write the key an d set permanent protection 1. write in fee0pro corresponding to the pages to be protected. 2. write the new (user defined) 32 bit key in fee0adr [ bits 31-16 ] and fee0dat [ bits 15-0 ]. 3. write 1,0 in fee0mod[6:5] and set fee0mod[3]. 4. run the write key command 0x0c in fee0con. to remove or modify the protection the same sequence can be used with a modified value of fee0pro. the sequence above is illustrated in the following example, this protects writing page 4 and page 5 of the flash/ee: int a = fee0sta; // ensure fee0sta is cleared fee0pro=0xfffffffb; // protect pages 4 and 5 fee0adr=0x66bb; // 32 bit key value [bits 31-16] fee0dat=0xaa55; // 32 bit key value [bits 15-0] fee0mod = 0x0048 // lock security sequence fee0con= 0x0c; // write key command while (fee0sta & 0x04){} // wait for command to finish aduc7033 flash/ee control interface the access to and control of the flash/ee memory on the aduc7033 is managed by an on-chip memory controller. the controller manages the flash/ee memory as two separate blocks (0 and 1). block 0 consists of the 32 kb flash/ee memory mapped from 0x00090000 to 0x00097fff (including the 2 kb kernel space which is reserved at the top of this block). block 1 consists of the 64 kb flash/ee memory mapped from 0x0008 0000 to 0x0008 ffff. it should be noted that mcu core can continue to execute code from one memory block while an active erase or program cycle is being carried out on the other block. if a command operates on the same block as the code currently executing, the core is halted until the command is completed, this also applies to code execution. user code, lin and jtag programming use the flash/ee control interface, which consists of the following mmrs : feexsta (x= 0 or 1): read only register, reflects the status of the flash/ee control interface feexmod (x= 0 or 1): sets the operating mode of the flash/ee control interface feexcon (x= 0 or 1): 8-bit command register. the commands are interpreted as described in table 13. feexdat (x= 0 or 1): 16-bit data register. feexadr (x= 0 or 1): 16-bit address register. feexsig (x= 0 or 1): holds the 24-bit code signature as a result of the signature command being initiated. feexhid (x= 0 or 1): protection mmr. controls read and write protection of the flash/ee memory code space. if previously configured via the feexpro register, feexhid may require a software key to enable access. feexpro (x= 0 or 1): a buffer of the feexhid register, which is used to store the feexhid value, so it is automatically downloaded to the feexhid registers on subsequent reset and power-on events. note: user software must ensure that the flash/ee controller has completed any erase or write cycle before the pll is powered down. if the pll is powered down before an erase or write cycle is completed, the flash/ee page or byte may be corrupted. the following sections describe in detail the bit designations of each of flash/ee control mmrs.
preliminary technical data aduc7030/aduc7033 rev. pre | page 33 of 150 fee0con and fee1con registers: name: fee0con and fee1con address: 0xffff0e08 and 0xffff0e88 default value: 0x07 access: read/write access function: these 8-bit registers are written by user code to control the operating modes of the flash/ee memory controllers for block0 (32 kb) and block1 (64 kb). table 17. command codes in fee0con and fee1con code command description (note x is 0 or 1 to designate flash/ee block 0 or 1) 0x00 * reserved reserved, this command should not be written by user code 0x01* single read load feexdat with the 16-bit data indexed by feexadr 0x02* single write write feexdat at the address pointed by feexadr. this operation takes 50 s. 0x03* erase-write erase the page indexed by feexadr and write feexdat at the location pointe d by feexadr. this operation takes 20ms 0x04* single verify compare the contents of the location pointed by feexadr to the data in f eexdat. the result of the comparison is returned in feexsta bit 1 0x05* single erase erase th e page indexed by feexadr 0x06* mass erase erase block0 (30kbyte) or block1 (64kbyte) of user space. the 2 kbyte kernel is protected. this operation takes 1.2 s to prevent accidental execution, a command sequence is re quired to execute this instruction, this is described below. 0x07 default command. 0x08 0x09 reserved reserved reserved, this command should not be written by user code. reserved, this command should not be written by user code. 0x0a reserved reserved, this command should not be written by user code. 0x0b signature fee0con: this command will result in a 24-bit lfsr based signature been generated and loaded into fee0sig. if fee0adr is less than 0x97800, this command will result in a 24-bit lfsr based signature of the user code space from the page specified in fee0adr upwards, incl uding the kernel, security bits and flash/ee key. if fee0adr is greater than 0x97800, the kernel and manu facturing data is signed. this operation takes 120us. fee1con: this command will result in a 24-bit lfsr based signatur e been generated, beginning at fee1adr and ending at the end of the 63.5 k block, and loaded into fee1sig. th e last page of this block is not included in the sign generation. 0x0c protect this command can be run only once. the value of feexpr o is saved and can be removed only with a mass erase (0x06) or with the key 0x0d reserved reserved, this command should not be written by user code. 0x0e reserved reserved, this command should not be written by user code. 0x0f ping no operation, interrupt generated. * the feexcon will always read 0x07 immediat ely after execution of any of these commands.
aduc7030/aduc7033 preliminary technical data rev. pre | page 34 of 150 command sequence for executing a mass erase giving the significance of the mass erase command, a specific code sequence must be executed to initiate this operation. 5. set bit 3 in feexmod. 6. write 0xffc3 in feexadr 7. write 0x3cff in feexdat 8. run the mass erase command 0x06 in feexcon this sequence is illustrated in the following example: int a = feexsta; // ensure feexsta is cleared feexmod = 0x08 feexadr = 0xffc3 feexdat = 0x3cff feexcon = 0x06; // mass-erase command while (feexsta & 0x04){} //wait for command to finish note: to run the mass erase command via fee0con, write protection on the lower 64kbytes must be disabled, that is, fee1hid/fee1pro are set to 0xffffffff. this can be done by first removing the protection or erasing the lower 64 kbytes first. fee0sta and fee1sta registers: name: fee0sta and fee1sta address: 0xffff0e00 and 0xffff0e80 default value: 0x20 access: read only function: these 8-bit read only registers can be read by user code and reflect the current status of the flash/ee memory controllers. table 18. fee0sta and fee1 sta mmr bit designations bit description (note x is 0 or 1 to designate flash/ee block 0 or 1) 7-4 not used these bits are not used and always read as 0. 3 flash/ee interrupt status bit set automatically when an interrupt occurs, that is, when a co mmand is complete and the flash/ ee interrupt enable bit in the feexmod register is set cleared automatically when the feexst a register is read by user code 2 flash/ee controller busy set automatically when the flash/ee controller is busy cleared automatically when the controller is not busy 1 command fail set automatically when a command written to feexcon completes unsuccessfully cleared automatically when the feexst a register is read by user code 0 command successful set automatically by mcu when a command is completed successfully. cleared automatically when the fee0sta register is read by user code
preliminary technical data aduc7030/aduc7033 rev. pre | page 35 of 150 fee0adr and fee1adr registers: name: fee0adr and fee1adr address: 0xffff0e10 and 0xffff0e90 default va lu e: 0x0000 (fee1adr). for fee0adr, please see page 148 access: read/write access function: this 16-bit register dictates the address upon which any flash/ee command executed via feexcon acts upon. fee0dat and fee1dat registers: name: fee0dat and fee1dat address: 0xffff0e0c and 0xffff0e8c default va lu e: 0x0000 access: read/write access function: this 16-bit register contains the data either read from or to be written to the flash/ee memory fee0mod and fee1mod registers: name: fee0mod and fee1mod address: 0xffff0e04 and 0xffff0e84 default value: 0x00 access: read/write access function: these registers are written by user code to configure the mode of operation of the flash/ee memory controllers. table 19. fee0mod and fee1mod mmr bit designations bit description (note: x is 0 or 1 to designate flash/ee block 0 or 1) 15-7 not used these bits are reserved for future functionalit y and should be written as 0 by user code 6, 5 flash/ee security lock bits these bits must be written as [6,5] = 1,0 to complete the flash/ee security protect sequence 4 flash/ee controller command complete interrupt enable this bit is set to 1 by user code to en able the flash/ee controller to generate an interrupt upon completion of a flash/ee comm and. this bit is cleared to disable the generation of a flas h/ee interrupt upon completion of a flash/ee command. 3 flash/ee erase/write enable set by user code to enable the flash/ee erase and write access via feexcon cleared by user code to disable the fl ash/ee erase and write access via feexcon 2 reserved and should be written as zero 1 flash/ee controller abort enable this bit is set to 1 by user code to enable the flash/ee controller abort functionality. 0 reserved and should be written as zero
aduc7030/aduc7033 preliminary technical data rev. pre | page 36 of 150 aduc7033 flash/ee memory security the 94 kbyte of flash/ee memory available to the user can be read and write protected using the ffe0hid and fee1hid registers. in block0, the fee0hid mmr protects the 30kbytes. bits 0-28 of this register protect pages 0-57 from writing. each bit protects 2 pages, that is, 1 kbytes. bits 29-30 protect pages 58 and 59 respectively, i.e. each bit write protects a single page of 512 bytes. the msb of this register (bit31) protects block0 from been read via jtag. the fee0pro register mirrors the bit definitions of the fee0hid mmr. the fee0pro mmr allows user code to lock the protection or security configuration of the flash/ee memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. this flexibility allows the user to set and test protection settings temporarily using the fee0hid mmr and subsequently lock the required protection configuration (using fee0pro) when shipping protection systems into the field. in block1 (64 k), the fee1hid mmr protects the 64kbytes. bits 0-29 of this register protect pages 0-119 from writing. each bit protects 4 pages, i.e. 2 kbytes. bit30 protect pages 120-127, i.e. bit 30 write protects eight pages of 512 bytes. the msb of this register (bit31) protects flash/ee block1, from been read via jtag. as with block0, fee1pro register mirrors the bit definitions of the fee1hid mmr. the fee1pro mmr is allows user code to lock the protection or security configuration of the flash/ee memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. block0, flash/ee memory protection registers: name: fee0hid and fee0pro address: 0xffff0e20 (for fee0hid) and 0xffff0e1c (for fee0pro) default value: 0xffffffff (for fee0hid) and 0x00000000 (for fee0pro) access: read/write access function: these registers are written by user code to configure the protection of the flash/ee memory. table 20. fee0hid and fee0 pro mmr bit designations bit description (note: x is 0 or 1 to designate flash/ee block 0 or 1) 31 read protection cleared by user to protect the 32kbyte fl ash/ee block code via jtag read access set by user to allow reading the 32kbyte flash/ee block code via jtag read access 30 write protection bit this bit is set by user code to unprotect protect page 59 this bit is cleared by user code write protect page 59 29 write protection bit this bit is set by user code to unprotect page 58 this bit is cleared by user code write protect page 58 28- 0 write protection bits when set by user code these bits will unprotect pages 0-57 of the 30-kbyte flash/ee code memory. each bit write protects 2 page s and each page consists of 512 bytes. when cleared by user code these bits will write protect pages 0-57 of the 30-kbyte fl ash/ee code memory. each bit write protect s 2 pages and each page consists of 512 bytes.
preliminary technical data aduc7030/aduc7033 rev. pre | page 37 of 150 block1, flash/ee memory protection registers: name: fee1hid and fee1pro address: 0xffff0ea0 (for fee1hid) and 0xffff0e9c (for fee1pro) default value: 0xffffffff (for fee1hid) and 0x00000000 (for fee1pro) access: read/write access function: these registers are written by user code to configure the protection of the flash/ee memory. table 21. fee1hid and fee1 pro mmr bit designations bit description 31 read protection cleared by user to protect the 64kbyte fl ash/ee block code via jtag read access set by user to allow reading the 64kbyte flash/ee block code via jtag read access 30 read protection this bit write protects 8 pages and each page consists of 512 bytes. when set by user code these bits will unprotec t pages 120-127 of the 64-kbyte flash/ee code memory. when cleared by user code these bits will write pr otect pages 120-127 of the 64-kbyte flash/ee code memory. 29 to 0 write protection bits when set by user code these bits will unprotect pages 0-119 of the 64-kbyte flash/ee code memo ry. each bit write protects 4 pages and each page consists of 512 bytes. when cleared by user code these bits wi ll write protect pages 0-119 of the 64-kbyte flash/ee code memory. each bit write protec ts 2 pages and each page consists of 512 bytes.
aduc7030/aduc7033 preliminary technical data rev. pre | page 38 of 150 in summary, there are three levels of protection: 1. temporary protection can be set and removed by writing directly into feexhid mmr. this register is volatile and therefore protection will only be in place while the part remains powered on. this protection is not reloaded after a power cycle. 2. keyed permanent protection can be set via feexpro which is used to lock the protection configuration. the software key used at the start of the required feexpro write sequence is saved once and must subsequently be used for any subsequent access of the feexhid or feexpro mmrs. a mass erase will set the key back to 0xffff but will also erase the entire user code space. 3. permanent protection can be set via feexpro, similarily to keyed permanent protection, the only difference being that the software key used is 0xdeaddead. once the feexpro write sequence is saved, only a mass erase will set the key back to 0xffffffff. this will also erase the entire user code space. sequence to write the key and set permanent protection: 1. write in feexpro corresponding to the pages to be protected. 2. write the new (user defined) 32 bit key in feexadr [ bits 31-16 ] and feexdat [ bits 15-0 ]. 3. write 1,0 in feexmod[6:5] and set feexmod[3]. 4. run the write key command 0x0c in feexcon. to remove or modify the protection the same sequence can be used with a modified value of feexpro. the sequence above is illustrated in the following example, this protects writing pages 4 and 5of the flash/ee: feexpro=0xfffffffb; //protect pages 4 and 5 feexadr=0x66bb; //32 bit key value [bits 31-16] feexdat=0xaa55; //32 bit key value [bits 15-0] feexmod = 0x0048 // lock security sequence feexcon= 0x0c; // write key command while (feexsta & 0x04){}//wait for command to finish flash/ee memory reliability the flash/ee memory array on the part is fully qualified for two key flash/ee memory characteristics: flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. a single endurance cycle is composed of four independent, sequential events, defined as: 1. initial page erase sequence. 2. read/verify sequence 3. byte program sequence 4. second read/verify sequence. in reliability qualification, every half word (16-bit wide) location of the three pages (top, middle and bottom) in the flash/ee memory is cycled 10,000 times from 0x0000 to 0xffff. as indicated in table 1, the parts flash/ee memory endurance qualification is carried out in accordance with jedec retention lifetime specification a117 the results allow the specification of a minimum endurance figure over supply, temperature of 10,000 cycles. retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the parts is qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature (t j = 85c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit, described previously, before data retention is characterized. this means that the flash/ee memory is guaranteed to retain its data for its fully specified retention lifetime every time the flash/ee memory is reprogrammed. also note that retention lifetime, based on an activation energy of 0.6 ev, derates with t j as shown in figure 12. 0 150 300 450 600 30 40 55 70 85 100 125 135 150 retention (years) junction temperature (c) 05994-012 figure 12. flash/ee memory data retention
preliminary technical data aduc7030/aduc7033 rev. pre | page 39 of 150 code execution time from sram and flash/ee this chapter describes sram and flash/ee access times during execution for applications where execution time is critical. execution from sram fetching instructions from sram takes one clock cycle as the access time of the sram is 2ns and a clock cycle is 49ns minimum. however, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in sram, or three cycle if the data is in flash/ee, one cycle to execute the instruction and two cycles to get the 32-bit data from flash/ee. a control flow instruction, for example a branch instruction will take one cycle to fetch but also two cycles to fill the pipeline with the new instructions. execution from flash/ee because the flash/ee width is 16-bit, execution from flash/ee cannot be done in one cycle, as from sram, when cd bit =0. also some dead time is needed before accessing data for any value of cd bits. in arm mode, where instructions are 32 bits, two extra cycles are needed to fetch any instruction when cd = 0 and in thumb mode, where instructions are 16 bits, one extra cycle is needed to fetch any instruction. timing is identical in both modes when executing instructions that involve using the flash/ee for data memory. if the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter and then four cycles are needed to fill the pipeline. a data processing instruction involving only core register doesnt require any extra clock cycle but if it involves data in flash/ee, an extra clock cycle is needed to decode the address of the data and two cycles to get the 32-bit data from flash/ee. an extra cycle must also be added before fetching another instruction. data transfer instruction are more complex and are summarized table 22. table 22. typical execution cycles in arm/thumb mode instructions fetch cycles dead time data access ld 2/1 1 2 ldh 2/1 1 1 ldm/push 2/1 n 2 n str 2/1 1 2 50 s strh 2/1 1 50 s strm/pop 2/1 n 2 n 50 s with 1 < n 16, n number of data to load or store in the multiple load/store instruction. by default, flash/ee code execution will be suspended during any flash/ee erase or write cycle. a page (512 bytes) erase cycle takes 20 ms and a write (16 bits) word command takes 50s. however, the flash/ee controller allows erase/write cycles to be aborted, if the arm core receives an enabled interrupt during the current flash/ee erase/write cycle. the arm7 can therefore immediately service the interrupt and then return to repeat the flash/ee command. the abort operation will typically take 10 clock cycles. if the abort operation is not feasible, it is possible to run flash/ee programming code and the relevant interrupt routines from sram, allowing the core to service the interrupt immediately.
aduc7030/aduc7033 preliminary technical data rev. pre | page 40 of 150 aduc7030/aduc7033 kernel the aduc7030/aduc7033 features an on-chip kernel resident in the top 2kbytes of the flash/ee code space. after any reset event, this kernel copies the factory calibrated data from the manufacturing data space, into the various on-chip peripherals. the peripherals calibrated by the kernel are as follows: power supply monitor (psm) precision, oscillator low power, oscillator reg_avdd/ reg_dvdd low power voltage reference normal mode voltage reference current adc (offset and gain ) voltage/ temperature adc (offset and gain ) user mmrs that can be modified by the kernel and differ from their por default values are as follows: r0-r15 gp0con/gp2con syschk adcmde/adc0con fee0adr/fee0con/feesig hvdat/hvcon hvcfg0/1 t3ld the aduc7030/aduc7033 also features an on-chip lin downloader. the operation of this download is detailed in aduc7030/aduc7033 series flash/ee programming via lin te chnote. a flow chart showing the execution of the kernel is shown in figure 13. the current revision of the kernel may be derived from sysser1, as described in table 93. for the duration of kernel execution, the watchdog timer is active with a timeout period of 30ms. this ensures that if an error occurs in the kernel, the aduc7030/aduc7033 will be reset. after a por reset, the watchdog timer is disabled once the kernel code is exited. after any other reset, the watchdog timer maintains user code configuration for the period of the kernel, and is refreshed just prior to kernel exit. a minimum watchdog period of 30ms is required. if lin download mode is entered the watchdog is periodically refreshed. normal kernel execution time, excluding lin download, is approximately 5ms. it is only possible to leave lin download mode via a reset. sram is not modified during normal kernel execution. sram is modified during lin download kernel execution.
preliminary technical data aduc7030/aduc7033 rev. pre | page 41 of 150 initialize on-chip peripherals to factory calibrated state flag page 0 error lin command jtag mode? ntrst = 1 key present? 0x14 = 0x27011970 page erased? 0x14 = 0xffffffff reset command checksum present? 0x14 = checksum execute user code no no no no yes yes yes no yes 05994-013 figure 13. aduc7030/aduc7033 kernel flowchart
aduc7030/aduc7033 preliminary technical data rev. pre | page 42 of 150 memory mapped registers the memory mapped register (mmr) space is mapped into the top 4 kbytes of the mcu memory space and accessed by indirect addressing, load and store commands, through the arm7 banked registers. an outline of the aduc7030/aduc7033s memory mapped register bank is shown in figure 14. the mmr space provides an interface between the cpu and all on-chip peripherals. all registers except the arm7 core registers (described in arm registers) reside in the mmr area. as can be seen from the detailed mmr map in table 23, the mmr data widths vary from 1 byte (8 bits) to 4 bytes (32 bits). the arm7 core can access any of the mmrs (single byte or multiple byte width registers) with a 32-bit read or write access. the resultant read for example, will be aligned per little endian format described earlier. however, errors will result if the arm7 core tries to access 4 byte (32 bit) mmrs with a 16-bit access. in the case of a (16-bit) write access to a 32-bit mmr, the (upper) 16 most significant bits will be written as 0s. more obviously, in the case of a 16-bit read access to a 32-bit mmr, only 16 of the mmr bits can be read. flash control interface gpio spi serial test interface hv interface lin/bsd hardware uart adc pll and oscillator control general purpose timer 4 watchdog timer 3 wake up timer 2 general purpose timer 1 timer 0 remap and system control interrupt controller 0xffffffff 0xffff1000 0xffff0e00 0xffff0d50 0xffff0d00 0xffff0a14 0xffff0a00 0xffff0894 0xffff0880 0xffff0810 0xffff0800 0xffff079c 0xffff0780 0xffff0730 0xffff0700 0xffff0580 0xffff0500 0xffff044c 0xffff0400 0xffff0394 0xffff0380 0xffff0370 0xffff0360 0xffff0350 0xffff0340 0xffff0334 0xffff0320 0xffff0318 0xffff0300 0xffff0244 0xffff0220 0xffff0110 0xffff0000 05994-014 figure 14. top level mmr map
preliminary technical data aduc7030/aduc7033 rev. pre | page 43 of 150 table 23. complete mmr list address name byte access type default value page description irq address base = 0xffff0000 0x0000 irqsta 4 r 0x00000000 80 active irq source 0x0004 irqsig 1 4 r 80 current state of all irq sources ( enabled and disabled ) 0x0008 irqen 4 rw 0x00000000 80 enabled irq sources 0x000c irqclr 4 w 80 mmr used to disabled irq sources 0x0010 swicfg 4 w 81 software interrupt configuration mmr 0x0100 fiqsta 4 r 0x00000000 80 active irq source 0x0104 fiqsig 1 4 r 80 current state of all irq sources ( enabled and disabled ) 0x0108 fiqen 4 rw 0x00000000 80 enabled irq sources 0x010c fiqclr 4 w 80 mmr used to disabled irq sources system control address base = 0xffff0200 0x0220 sysmap0 1 rw 25 remap control register 0x0230 rststa 1 rw 26 reset status mmr 0x0234 rstclr 1 w 26 rststa clear mmr 0x0238 sysser0 2 4 rw 146 system serial number 0 0x023c sysser1 2 4 rw 147 system serial number 1 0x0240 syschk 2 4 rw 147 kernel checksum timer address base = 0xffff0300 0x0300 t0ld 2 rw 0x0000 85 timer 0 load register 0x0304 t0val0 2 r 0x0000 83 timer 0 value register 0 0x0308 t0val1 4 r 0x00000000 83 timer 0 value register 1 0x030c t0con 4 rw 0x00000000 84 timer 0 control mmr 0x0310 t0clri 1 w 85 timer 0 interrupt clear register 0x0314 t0cap 2 rw 0x0000 83 timer 0 capture register 0x0320 t1ld 4 rw 0x00000000 86 timer 1 load register 0x0324 t1val 4 r 0xffffffff 86 timer 1 value register 0x0328 t1con 4 rw 0x01000000 87 timer 1 control mmr 0x032c t1clri 1 w 86 timer 1 interrupt clear register 0x0330 t1cap 4 r 0x00000000 87 timer 1 capture register
aduc7030/aduc7033 preliminary technical data rev. pre | page 44 of 150 address name byte access type default value page description 0x0340 t2ld 4 rw 0x00000000 88 timer 2 load register 0x0344 t2val 4 r 0xffffffff 88 timer 2 value register 0x0348 t2con 2 rw 0x0000 89 timer 2 control mmr 0x034c t2clri 1 w 88 timer 2 interrupt clear register 0x0360 t3ld 2 rw 0x0040 90 timer 3 load register 0x0364 t3val 2 r 0x0040 91 timer 3 value register 0x0368 t3con 2 rw 0x0000 91 timer 3 control mmr 0x036c t3clri 2 1 w 91 timer 3 interrupt clear register 0x0380 t4ld 2 rw 0x0000 92 timer 4 load register 0x0384 t4val 2 r 0xffff 92 timer 4 value register 0x0388 t4con 4 rw 0x00000000 93 timer 4 control mmr 0x038c t4clri 1 w 92 timer 4 interrupt clear register 0x0390 t4cap 2 r 0x0000 92 timer 4 capture register pll base address = 0xffff0400 0x0400 pllsta 4 r 74 pll status mmr 0x0404 powkey0 4 w 75 powcon pre write key 0x0408 powcon 1 rw 0x79 76 power control and core speed control register 0x040c powkey1 4 w 75 powcon post write key 0x0410 pllkey0 4 w 75 pllcon pre write key 0x0414 pllcon 1 rw 0x00 75 pll clock source selection mmr 0x0418 pllkey1 4 w 75 pllcon post write key 0x042c osc0trm 1 rw 0xx8 78 low power oscillator trim bits mmr. 0x0440 osc0con 1 rw 0x00 78 low power oscillator calibration control mmr 0x0444 osc0sta 1 r 0x00 79 low power oscillator calibration status mmr 0x0448 0sc0val0 2 r 0x0000 79 low power oscillator calibration counter 0 mmr 0x044c osc0val1 2 r 0x0000 79 low power oscillator calibration counter 1 mmr adc address base = 0xffff0500 0x0500 adcsta 2 r 0x0000 53 adc status mmr 0x0504 adcmski 1 rw 0x00 55 adc interrupt source enable mmr 0x0508 adcmde 1 rw 0x00 55 adc mode register
preliminary technical data aduc7030/aduc7033 rev. pre | page 45 of 150 address name byte access type default value page description 0x050c adc0con 2 rw 0x0000 57 current adc control mmr 0x0510 adc1con 2 rw 0x0000 58 v/t adc control mmr 0x0518 adcflt 2 rw 0x0007 59 adc filter control mmr 0x051c adccfg 1 rw 0x00 61 adc configuration mmr 0x0520 adc0dat 2 r 0x0000 62 current adc result mmr 0x0524 adc1dat 2 r 0x0000 62 v adc result mmr 0x0528 adc2dat 2 r 0x0000 62 t adc result mmr 0x0530 adc0of 2 2 rw 62 current adc offset mmr 0x0534 adc1of 2 2 rw 63 voltage adc offset mmr 0x0538 adc2of 2 2 rw 63 temperature adc offset mmr 0x053c adc0gn 2 2 rw 63 current adc gain mmr 0x0540 adc1gn 2 2 rw 64 voltage adc gain mmr 0x0544 adc2gn 2 2 rw 64 temperature adc gain mmr 0x0548 adc0rcl 2 rw 0x0001 64 current adc result count limit 0x054c adc0rcv 2 r 0x0000 64 current adc result count value 0x0550 adc0th 2 rw 0x0000 65 current adc result threshold 0x0554 adc0tcl 1 rw 0x01 65 current adc result threshold count limit 0x0558 adc0thv 1 r 0x00 65 current adc result threshold count limit value 0x055c adc0acc 4 r 0x00000000 65 current adc result accumulator 0x057c adcref 2 2 rw 66 low power mode voltage reference scaling factor uart base address = 0xffff0700 0x0700 comtx 1 w 118 uart transmit register comrx 1 r 0x00 118 uart receive register comdiv0 1 rw 0x00 118 uart standard baud rate generator divisor value 0 0x0704 comien0 1 rw 0x00 122 uart interrupt enable mmr 0 comdiv1 1 r/w 0x00 118 uart standard baud rate generator divisor value 1 0x0708 comiid0 1 r 0x01 122 uart interrupt identification 0 0x070c comcon0 1 rw 0x00 119 uart control register 0 0x0710 comcon1 1 rw 0x00 120 uart control register 1 0x0714 comsta0 1 r 0x60 121 uart status register 0
aduc7030/aduc7033 preliminary technical data rev. pre | page 46 of 150 address name byte access type default value page description 0x072c comdiv2 2 rw 0x0000 123 uart fractional divider mmr lin hardware sync base address = 0xffff0780 0x0780 lhssta 1 r 0x00 133 lhs status mmr 0x0784 lhscon0 2 r/w 0x0000 134 lhs control mmr 0 0x0788 lhsval0 2 r/w 0x0000 136 lhs timer 0 mmr 0x078c lhscon1 1 r/w 0x32 136 lhs control mmr 1 0x0790 lhsval1 2 r/w 0x0000 137 lhs timer 1 mmr 0x0794 lhscap 1 r 0x0000 142 lhs capture mmr 0x0798 lhscmp 2 r/w 0x0000 142 lhs compare mmr high voltage interface base address = 0xffff0800 0x0804 hvcon 1 rw 111 high voltage interface control mmr 0x080c hvdat 1 rw 110 high voltage interface data mmr sti base address = 0xffff0880 0x0880 stikey0 4 w 128 sticon pre write key 0x0884 sticon 2 rw 0x0000 129 serial test interface control mmr 0x0888 stikey1 4 w 128 sticon post write key 0x088c stidat0 2 rw 0x0000 128 sti data mmr 0 0x0890 stidat1 2 rw 0x0000 129 sti data mmr 1 0x0894 stidat2 2 rw 0x0000 129 sti data mmr 2 spi base address = 0xffff0a00 0x0a00 spista 1 r 0x00 126 spi status mmr 0x0a04 spirx 1 r 0x00 126 spi receive mmr 0x0a08 spitx 1 w 126 spi transmit mmr 0x0a0c spidiv 1 rw 0x1b 127 spi baud rate select mmr 0x0a10 spicon 2 rw 0x00 125 spi control mmr gpio base address = 0xffff0d00 0x0d 00 gp0con 4 rw 0x11100000 96 gpio port 0 control mmr 0x0d 04 gp1con 4 rw 0x10000000 97 gpio port 1 control mmr 0x0d 08 gp2con 4 rw 0x01000000 98 gpio port 2 control mmr 0x0d 20 gp0dat 3 4 rw 0x000000xx 99 gpio port 0 data control mmr
preliminary technical data aduc7030/aduc7033 rev. pre | page 47 of 150 address name byte access type default value page description 0x0d 24 gp0set 4 w 102 gpio port 0 data set mmr 0x0d 28 gp0clr 4 w 105 gpio port 0 data clear mmr 0x0d 30 gp1dat 3 4 rw 0x000000xx 100 gpio port 1 data control mmr 0x0d 34 gp1set 4 w 103 gpio port 1 data set mmr 0x0d 38 gp1clr 4 w 106 gpio port 1 data clear mmr 0x0d 40 gp2dat 3 4 rw 0x000000xx 101 gpio port 2 data control mmr 0x0d 44 gp2set 4 w 104 gpio port 2 data set mmr 0x0d 48 gp2clr 4 w 107 gpio port 2 data clear mmr flash/ee base address = 0xffff0e00 0x0e00 fee0sta 1 r 0x20 34 flash/ee status mmr 0x0e04 fee0mod 1 rw 0x00 35 flash/ee control mmr 0x0e08 fee0con 1 rw 0x07 33 flash/ee control mmr 0x0e0c fee0dat 2 rw 0x0000 35 flash/ee data mmr 0x0e10 fee0adr 2 rw 35 flash/ee address mmr 0x0e18 fee0sig 3 r 0xffffff flash/ee lfsr mmr 0x0e1c fee0pro 4 rw 0x00000000 36 flash/ee protection mmr 0x0e20 fee0hid 4 rw 0xffffffff 36 flash/ee protection mmr 0x0e80 fee1sta 4 1 r 0x20 34 flash/ee status mmr 0x0e84 fee1mod 4 1 rw 0x00 35 flash/ee control mmr 0x0e88 fee1con 4 1 rw 0x07 33 flash/ee control mmr 0x0e8c fee1dat 4 2 rw 0x0000 35 flash/ee data mmr 0x0e90 fee1adr 4 2 rw 0x0000 35 flash/ee address mmr 0x0e98 fee1sig 4 3 r 0xffffff flash/ee lfsr mmr 0x0e9c fee1pro 4 4 rw 0x00000000 37 flash/ee protection mmr 0x0ea0 fee1hid 4 4 rw 0xffffffff 37 flash/ee protection mmr 1 depends on the level on the external interrupt pins gp0, gp5, gp7 and gp8 2 updated by kernel 3 depends on the level on the external gpio pins 4 only available on the aduc7033
aduc7030/aduc7033 preliminary technical data rev. pre | page 48 of 150 16-bit ?? analog to digital converters the aduc7030/aduc7033 incorporate two independent sigma-delta adcs namely, the current channel adc (i-adc) and the voltage/temperature channel adc (v/t-adc). these precision measurement channels integrate on-chip buffering, programmable gain amplifier, 16-bit sigma-delta modulators, and digital filtering and are intended for the precision measurement of current, voltage, and temperature variables in 12 v automotive battery systems. current channel adc (i-adc) this adc is intended to convert battery current sensed through an external 100 ? shunt resistor. on-chip programmable gain mean the i-adc can be configured to accommodate battery current levels from 1a to 1500a as shown in figure 15, the i-adc employs a sigma-delta conversion technique to realize 16 bits of no missing codes performance. the sigma-delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. a modified sinc3 programmable low- pass filter is then employed to decimate the modulator output data stream to give a valid 16-bit data conversion result at programmable output rates from 4 hz to 8 kkhz in normal mode and 1 hz to 2 khz in low power mode. the i-adc also incorporates counter, comparator and accumulator logic. this allows the i-adc result to generate an interrupt after a predefined number of conversions have elapsed or if the i-adc result exceeds a programmable threshold value. a fast adc-over-range feature is also supported. once enabled, a 32-bit accumulator au tomatically sums the 16-bit i- adc results. the time to a first valid (fully settled) result on the current channel is three adc conversion cycles with chop mode turned off and two adc conversion cycles with chop mode turned on.
preliminary technical data aduc7030/aduc7033 rev. pre | page 49 of 150 pga adc threshold adc result output format buf chop chop analog input diagnostic current sources two 50a iin+ and iin? current sources. analog input diagnostic voltage source vref/136 voltage input. analog input programmable chopping the inputs are alternately reversed through the conversion cycle. - ? adc the - ? architecture ensures 16 bits no missing codes. output average as part of the chopping implementation, each data-word output from the filter is summed and averaged with its predecessor. adc fast overrange generates an adc interrupt if the current input is grossly over-ranged. adc accumulator accumulated the adc result. programmable gain amplifier the programmable gain amplifier allows eight bipolar input ranges from 2.3mv to 1.2v (int v ref = +1.2v). - ? modulator the modulator provides a high frequency 1-bit data stream (the output of which is also chopped) to the digital filter, the duty cycle of which represents the sampled analog input voltage. in+ in? vref/136 gnd reg_avdd reg_avdd - ? a/d converter - ? modulator programmable digital filter output average offset coefficient gain coefficient adc interrupt adc result accumulator adc result adc result counter threshold counter adc interrupt generator generates an adc result from any one of four sources. adc result counter counts adc results, generates an interrupt on counter overflow. threshold counter counts up if adc results>threshold counts down/reset if adc result aduc7030/aduc7033 preliminary technical data rev. pre | page 50 of 150 voltage/temperature channel adc (v/t- adc) this voltage/temperature channel adc (v/t-adc) is intended to convert additional battery parameters such as voltage and temperature. the input to this channel can be multiplexed from one of three input sources, namely external voltage, external temperature sensor circuit and on-chip temperature sensor. as with the current channel adc described previously, the v/t-adc employs an identical sigma-delta conversion technique, including a modified sinc3 low-pass filter to give a valid 16-bit data conversion result at programmable output rates from 4hz to 8 khz. an external rc filter network is not required as this is implemented internally in the voltage channel. the external battery voltage (vbat) is routed to the adc input via an on-chip high voltage, (divide by 24) resistive attenuator. this must be enabled/disabled via hvcfg1[7]. the battery temperature can be derived via the on chip temperature sensor or an external temperature sensor input. the time to a first valid (fully settled) result after an input channel switch on the voltage/temperature channel is three adc conversion cycles with chop mode turned off. this adc is again buffered but unlike the current channel has a fixed input range of 0v to v ref on vtemp+ and 0v to 28.8v on vbat (assuming an internal 1.2v reference). a top level overview of this adc signal chain is shown in figure 16. 05994-016 adc result output format chop - ? adc the - ? architecture ensures 16 bits no missing codes. output average as part of the chopping implementation, each data-word output from the filter is summed and averaged with its predecessor. - ? modulator the modulator provides a high frequency 1-bit data stream (the output of which is also chopped) to the digital filter, the duty cycle of which represents the sampled analog input voltage. - ? a/d converter - ? modulator programmable digital filter output average offset coefficient gain coefficient adc interrupt generator generates an adc interrupt once a voltage or temperature conversion is completed. precision reference the internal 5ppm/c reference is routed to the adc by default. an external reference on the vref pin can also be selected. buf internal temp buf chop mux internal reference vref programmable digital filter the sinc 3 filter removes quantization noise introduced by the modulator. the update rate and bandwidth of this filter are programmable via the adcflt mmr. output scaling the output word from the digital filter is scaled by the calibration coefficients before being provided as the conversion result. vbat vtemp 45r 2r 1r adc interrupt to voltage or temperature data mmr differential attenuator divide by 24, input attenuator buffer amplifiers the buffer amplifiers presents a high impedance input stage for the analog input. analog input programmable chopping the inputs are alternately reversed through the conversion cycle. figure 16. voltage/ temperature adc, top level overview
preliminary technical data aduc7030/aduc7033 rev. pre | page 51 of 150 adc ground switch the aduc7030/aduc7033 features an integrated ground switch pin, gnd_sw, pin15. this switch allows the user to dynamically disconnect ground from external devices. it allows either a direct connection to ground, or a connection to ground via a 20 k ? . this additional resistor may be used to reduce the number of external components required for an ntc circuit. the ground switch feature may be used for reducing power consumption on application specific boards. an example application is shown in figure 17. this diagram shows an external ntc used in two modes, one using the internal 20 k ? resistor, and the second showing a direct connection to ground, via the gnd_sw. adccfg[7] controls the connection of the ground switch to ground and adcmde[6] controls the gnd_sw resistance. the possible combinations are shown in table 24. table 24. gnd_sw configuration adccfg[7] adcmde[6] gnd_sw 0 0 floating 0 1 floating 1 0 direct connection to ground 1 1 connected to ground via 20 k? resistor 05994-017 r ref reg_avdd vtemp ntc 20k ? reg_avdd vtemp ntc figure 17. example external temperature sensor circuits 05994-018 20k ? gnd_sw adcmde[6] adccfg[7] figure 18. internal ground switch configuration
aduc7030/aduc7033 preliminary technical data rev. pre | page 52 of 150 adc noise performance tables table 25, table 26 and table 27 below show the output rms noise in v for some typical output update rates on the i and v/t adc s. the numbers are typical and are generated at a differential input voltage of 0 v. the output rms noise is specified as the standard deviation (or 1 x sigma) of the distribution of adc output codes collected when the adc input voltage is at a dc voltage. it is expressed as v rms. table 25. current channel adc, normal power mode, typical output rms noise (v) adc input range adcflt data update rate 2.3mv (512) 4.6mv (256) 4.68mv (128) 18.75mv (64) 37.5mv (32) 75mv (16) 150mv (8) 300mv (4*) 600mv (2*) 1.2v (1*) 0xbf1d 4 hz 0.040 0.040 0.043 0.045 0.087 0.175 0.35 0.7 1.4 2.8 0x961f 10 hz 0.060 0.060 0.060 0.065 0.087 0.175 0.35 0.7 1.4 2.8 0x007f 50 hz 0.142 0.142 0.144 0.145 0.170 0.305 0.380 0.7 2.3 2.8 0x0007 1 khz 0.620 0.620 0.625 0.625 0.770 1.310 1.650 2.520 7.600 7.600 0x0000 8 khz 2.000 2.000 2.000 2.000 2.650 4.960 8.020 15.0 55.0 55.0 *please note that the maximum absolute input voltage allowed is -200mv to 300mv relative to ground table 26. voltage channel adc, typical output rms noise (referred to adc voltage attenuator input)( v) adcflt data update rate 28.8v adc input range 0xbf1d 4hz 65 0x961f 10hz 65 0x0007 1khz 180 0x0000 8khz 1600 table 27. temperature channel ad c, typical output rms noise ( v) adcflt data update rate 0 to 1.2 v adc input range 0xbf1d 4 hz 2.8 0x961f 10 hz 2.8 0x0007 1 khz 7.5 0x0000 8 khz 55
preliminary technical data aduc7030/aduc7033 rev. pre | page 53 of 150 adc mmr interface the adc is controlled and configured via a number of mmrs that are described in detail in the following pages: adc status register: name: adcsta address: 0xffff0500 default value: 0x0000 access: read only function: this read only register holds general status information related to the mode of operation or current status of the aduc7030/aduc7033 adcs. table 28. adcsta mmr bit designations bit description 15 adc calibration status this bit is set automatically in hardware to indicate an adc calibration cycle has been completed. this bit is cleared after adcmde is written to. 14 adc temperature conversion error this bit is set automatically in hardware to indicate that a te mperature conversion over-range or under-range has occurred. the conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this case. this bit will be cleared when a valid (in-range) temperatur e conversion result is written to the adc2dat register. 13 adc voltage conversion error this bit is set automatically in hardware to indicate that a voltage conversion over-range or under-range has occurred. the conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this case. this bit will be cleared when a valid (in-range) voltage conversion result is written to the adc1dat register. 12 adc current conversion error this bit is set automatically in hardware to indicate that a cu rrent conversion over-range or under-range has occurred. the con version result will be clamped to negative full-scale (under-range er ror) or positive full-scale (over-range error) in this case. this bit will be cleared when a valid (in-range) current conversion result is written to the adc0dat register. 11-5 not used this bit is reserved for future functionalit y and should not be monitored by user code 4 current channel adc comparator threshold this bit is only valid if the current channel adc comparator is enabled via the adccfg mmr. this bit is set by hardware if the absolute value of the i-adc conversion resu lt exceeds the value written in the adc0th mmr. if the adc threshold counter is used (adc0tcl), this bit is only set once the specified number of i-adc conversions equals the value in the adc0thv mmr. 3 current channel adc over-range bit if the over-range detect function is enabled via the adccfg mmr, this bit is set by hardware if the i-adc input is grossly (>30 % approx.) over-ranged. this bit is updated every 125secs. once set, this bit can only be cleared by software when adccfg[2] is cleared to disable the function, or the ad c gain is changed via the adc0con mmr. 2 temperature conversion result ready bit if the temperature channel adc is enabled, th is bit is set by hardware as soon as a valid temperature conversion result is writ ten in the temperature data register (adc2dat mmr). it is also set at the end of a calibration this bit is cleared by reading either adc2dat or adc0dat. 1 voltage conversion result ready bit if the voltage channel adc is enabled, this bit is set by hardware as soon as a valid voltage conv ersion result is written in t he voltage data register (adc1dat mmr) it is also set at the end of a calibration this bit is cleared by reading either adc1dat or adc0dat. 0 current conversion result ready bit if the current channel adc is enabled, this bit is set by hardware as soon as a valid current conversion result is written in t he current data register (adc0dat mmr) it is also set at the end of a calibration this bit is cleared by reading adc0dat. notes 1. all bits defined in the top 8 msbs (bits 8C15) of the mmr are used as flags only and will not generate interrupts 2. all bits defined in the lower 8 lsbs (bits 0-7) of this mmr are logic ored to produce a single adc interrupt to the mcu cor e.
aduc7030/aduc7033 preliminary technical data rev. pre | page 54 of 150 3. in response to an adc interrupt, user code should interrogate the adcsta mmr to determine the source of the interrupt. 4. each adc interrupt source can be individually masked via the adcmski mmr described below 5. all adc result ready bits are cleared by a read of the adc0dat mmr. if the current channel adc is not enabled, all adc resul t ready bits are cleared by a read of the adc1dat or adc2dat mmrs. 6. to ensure that i-adc and v/t-adc conver sion data are synchronous, user code sh ould first read the adc1dat mmr and then adc0dat mmr. 7. new adc conversion results will not be written to the adcxdat mmrs unless the respective adc result ready bits are first cle ared. the only exception to this rule is data co nversion result updates when the arm core is powered down. in this mode, adcxdat regi sters will always contain the most recent adc conversion result even though the ready bits have not been cleared.
preliminary technical data aduc7030/aduc7033 rev. pre | page 55 of 150 adc interrupt mask register: name: adcmski address: 0xffff0504 default value: 0x00 access: read/write function: this register allows the adc interrupt sources to be enabled individually. the bits position in this register are the same as the lower 8-bits in the adcsta mmr. if a bit is set by user code to a 1, the respective interrupt is enabled. by default all bits are 0 meaning all adc interrupt sources are disabled. adc mode register: name: adcmde address: 0xffff0508 default value: 0x00 access: read/write function: the adc mode mmr is an 8-bit register that configures the mode of operation of the adc sub-system. table 29. adcmde mmr bit designations bit description 7 not used this bit is reserved for future function ality and be written as 0 by user code 6 20k ? resistor select: this bit is set to 1 to select the 20 k ? resistor as shown in figure 18 this bit is set to 0 to select the direct path to ground as shown in figure 18 (default). 5 low power mode reference select: this bit is set to 1 to enable the precision voltage reference in either low power mode or low power plus mode. this will incre ase current consumption. this bit is set to 0 to enable the low power voltage reference in either low power mode or low power plus mode (default). 4-3 adc power mode configuration 0, 0 adc normal mode if enabled, the adc will operate with normal current consumption yielding optimum electrical performance 0, 1 adc low power mode if enabled, the i-adc will operate with reduced current consumption. this limitation is current consumption is achieved, (at the expense of adc noise performance) by fixing the gain to 128 and using the on-chip low power (131khz) oscillator to drive the adc circuits directly. 1, 0 adc low power-plus mode if enabled, the adc will again operate with reduced current consumption. in this mode, th e gain is fixed to 512 and the current consumed is 200ua (approx.) more than adc low po wer mode above. the additional current consumed also ensures adc noise performance is better th an that achieved in adc low power mode. 1, 1 not defined 2-0 adc operation mode configuration 0, 0, 0 adc power-down mode all adc circuits (including internal reference) are powered-down 0, 0, 1 adc continuous conversion mode in this mode, any enabled adc will continuously convert. 0, 1, 0 adc single conversion mode in this mode, any enabled adc will perform a single conversion. the adc will enter idle mode once the single shot conversion is complete. a single conversion will take 2/3 adc clock cycles depending on the chop mode. 0, 1, 1 adc idle mode in this mode, the adc is fully powered on but is held in reset 1, 0, 0 adc self-offset calibration in this mode, an offset calibration is performed on any en abled adc using an internally generated 0v. the calibration is carried out at the user programmed adc se ttings, therefore, as with a normal sing le adc conversion, it will take 2/3 adc conversion cycles before a fully settled calibration result is ready. the calibration result is automatically written to the
aduc7030/aduc7033 preliminary technical data rev. pre | page 56 of 150 bit description adcxof mmr of the respective adc. the adc returns to idle mode and the calibration and conversion ready status bits are set at the end of an offset calibration cycle. 1, 0, 1 adc self gain calibration in this mode, a gain calibration against an internal re ference voltage is performed on all enabled adcs. a gain calibration is a 2-stage process and takes twice the time of an offset calibration. the calibr ation result is automatically written to the adcxgn mmr of the respective adc. the adc returns to idle mode and the calibration and conversion ready status bits are set at the end of a gain ca libration cycle. an adc self-gain calibration should only be carried out on the current channel adc while pre-prog rammed, factory calibration coefficients (downloaded automatically from internal flash/ee) should be used for volt age temperature measurements. if an external ntc is used, an adc self calibration should be done on the temperature channel. 1, 1, 0 adc system zero-scale calibration in this mode, a zero-scale calibration is performed on enabled adc channels against an external zero-scale voltage driven at the adc input pins. the calibration is ca rried out at the user programmed adc settings, therefore, as with a normal single adc conversion, it will take 3 adc conver sion cycles before a fully settled calibration result is ready. 1, 1, 1 adc system full-scale calibration in this mode, a full-scale calibration is performed on enabled adc channels against an external full-scale voltage driven at the adc input pins.
preliminary technical data aduc7030/aduc7033 rev. pre | page 57 of 150 current channel adc control register: name: adc0con address: 0xffff050c default value: 0x0000 access: read/write function: the current channel adc control mmr is a 16-bit register that is used to configure the i-adc. note: if the current adc is reconfigured via adc0con, the voltage and temperature adcs are also reset. table 30. adc0con mmr bit designations bit description 15 current channel adc enable this bit is set to 1 by user code to enable the i-adc clearing this bit to 0, powers down the i-adc and rese ts the respective adc ready bit in the adcsta mmr to 0 14, 13 iin current source enable 0, 0 current sources off 0, 1 enable 50 a current source on iin+ 1, 0 enable 50 a current source on iin- 1, 1 enable 50 a current source on both iin- and iin+ 12C 10 not used these bits are reserved for future functi onality and should be written as zero 9 current channel adc output coding this bit is set to 1 by user code to configure i-adc output coding as unipolar this bit is cleared to 0 by user code to co nfigure i-adc output coding as 2s complement 8 not used these bits are reserved for future functi onality and should be written as zero 7, 6 current channel adc input select 0, 0 iin+, iin- 0, 1 iin-, iin- diagnostic, internal short configuration 1, 0 v ref /136, 0v diagnostic, test voltage for gain settings <= 128 note: if (reg_avdd, agnd) divided by 2 reference is selected, reg_avdd is used for v ref in this mode. this will lead to adc0dat scaled by two 1, 1 not defined 5, 4 current channel adc reference select 0, 0 internal, 1.2v precision reference selected. in adc low power mode, the voltage reference selection is controlled by adcmde[5] 0, 1 external reference inputs (vref, gnd_sw) selected 1, 0 external reference inputs divided by 2 (vref, gnd_sw)/2 selected, this allows an external reference up to reg_avdd 1, 1 (reg_avdd, agnd) divided by 2 selected 3 - 0 current channel adc gain select (note, nominal i-adc full-scale input voltage = (v ref /gain) 0, 0, 0, 0 i-adc gain =1 0, 0, 0, 1 i-adc gain =2 0, 0, 1, 0 i-adc gain =4 0, 0, 1, 1 i-adc gain =8 0, 1, 0, 0 i-adc gain =16 0, 1, 0, 1 i-adc gain =32 0, 1, 1, 0 i-adc gain =64 0, 1, 1, 1 i-adc gain =128 1, 0, 0, 0 i-adc gain =256 1, 0, 0, 1 i-adc gain =512 1, x, x, x i-adc gain is undefined
aduc7030/aduc7033 preliminary technical data rev. pre | page 58 of 150 voltage/temperature channel adc control register: name: adc1con address: 0xffff0510 default value: 0x0000 access: read/write function: the voltage/temperature channel adc control mmr is a 16-bit register that is used to configure the v/t-adc. note: when enabling/disabling the voltage/temperature adc, the voltage attenuator must also be enabled/disabled via hvcfg1[7]. table 31. adc1con mmr bit designations bit description 15 voltage/temperature channel adc enable this bit is set to 1 by user code to enable the v/t-adc. when enabling/disabling the voltage channel, the voltage attenuator must also be enabled/disabled via hvcfg1[7] if measuring battery voltage. clearing this bit to 0, powers down the v/t-adc. 14, 13 vtemp current source enable 0, 0 current sources off 0, 1 enable 50a current source on vtemp+ 1, 0 enable 50a current source on gnd_sw 1, 1 enable 50a current source on both vtemp+ and gnd_sw 12C 10 not used. these bits are reserved for future functionality and should not be modified by user code 9 voltage/temperature channel adc output coding this bit is set to 1 by user code to configure v/t-adc output coding as unipolar this bit is cleared to 0 by user code to conf igure v/t -adc output coding as 2s complement 8 not used. this bit is reserved for future functionality and should be written as 0 by user code 7, 6 voltage/temperature channel adc input select 0, 0 vbat/24, agnd vbat attenuator selected 0, 1 vtemp, gnd_sw external temperature input selected, conversion result written to adc2dat 1, 0 internal sensor internal temperature sensor input selected, conversion result written to adc2dat 1, 1 internal short shorted input 5, 4 voltage temperature channel adc reference select 0, 0 internal, 1.2v precision reference selected. 0, 1 external reference inputs (vref, gnd_sw) selected. 1, 0 external reference inputs divided by 2 (vref, gnd_sw)/2 selected. this allows an external reference up to reg_avdd 1, 1 (reg_avdd, agnd) / 2 selected for the voltage channel. (reg_avdd, gnd_sw) / 2 selected for the temperature channel. 3 C 0 not used. these bits are reserved for future functionality and should not be written as 0 by user code
preliminary technical data aduc7030/aduc7033 rev. pre | page 59 of 150 adc filter register: name: adcflt address: 0xffff0518 default value: 0x0007 access: read/write function: the adc filter mmr is an 16-bit register that controls the speed and resolution of the on-chip adcs. note: if adcflt is modified, the current and voltage/temperature adcs are reset. table 32. adcflt mmr bit designations bit description 15 chop enable set by user to enable system chopping of all active adcs. when this bit is set the adc will have very low offset errors and dri ft but the adc output rate will be reduced by a factor of 3 if af=0 (see sinc3 decimation factor bits below). if af > 0, then adc output update rate will be the same with chop on or off. when chop is en abled, the settling time is 2 output periods. 14 running average set by user to enable a running average by 2 function reduci ng adc noise. this function is automatically enabled when chopping is active. it is an optional feature when chopping is inactive and if enabled (when ch opping is inactive) does not reduce adc output rate but will increase th e settling time by 1 conversion period. cleared by user to disable the running average function. 13 - 8 averaging factor ( af ) the value written to these bits is use to implement a programmable 1 st order sinc post filter. the averaging factor can further reduce adc noise at the expense of output rate as described in sinc decimation factor bits below. 7 sinc3 modify set by user to modify the standard sinc3 frequency response to increase the filter stopband rejection by 5dbs approx. this is achieved by inserting a seco nd notch (notch2) at f notch2 = 1.333 * f notch where f notch is the location of the 1 st notch in the response. 6 C 0 sinc3 decimation factor (sf) the value (sf) written in these bits controls the over sampling (decimation factor) of the sinc3 filter. the output rate from t he sinc3 filter is given by f adc = ( 512,000 / ( [sf+1] x 64 )) hz when the chop bit (bit#15 above) = 0 and af=0 (note af = averaging factor) note : this is valid for all sf values <= 125 for sf= 126, f adc is forced to 60hz for sf= 127, f adc is forced to 50hz for information on calculating the f adc for sf (other than 126 and 127) and af values please refer to table 33. notes: - due to limitations on the digital filter internal data-path, there are some limita tions on the combinations of sf (sinc3 decimation factor) and af (averaging factor ) that can be used to generate a requir ed adc output rate. th is restriction limits the minimum adc update in normal power mo de to 4hz or 1hz in low power mode. - in low power mode and low power-plus mode, the adc is dri ven directly by the low power oscillator (131khz) and not 512khz. all f adc calculations should be divided by 4 (approx).
aduc7030/aduc7033 preliminary technical data rev. pre | page 60 of 150 table 33. adc conversion rates and settling times chop enabled averaging factor running average f adc *t settling no no no 64 * ] 1 [ 512000 + sf adc f 3 no no yes 64 * ] 1 [ 512000 + sf adc f 4 no yes no ] 3 [ * 64 * ] 1 [ 512000 af sf + + adc f 1 no yes yes ] 3 [ * 64 * ] 1 [ 512000 af sf + + adc f 2 yes n/a n/a ] 3 [ * 64 * ] 1 [ 512000 af sf + + adc f 2 *an additional time of approximately 60s per adc is required before the first adc is available. table 34. allowable combinations of sf and af af range sf 0 1 to 7 8 to63 0-31 32-63 64-127
preliminary technical data aduc7030/aduc7033 rev. pre | page 61 of 150 adc configuration register: name: adccfg address: 0xffff051c default value: 0x00 access: read/write function: the 8-bit adc configuration mmr controls extended functionality related to the on-chip adcs. table 35. adccfg mmr bit designations bit description 7 analog ground switch enable this bit is set to 1 by user software to connect the external gnd_sw pin (pin#15) to an internal analog ground reference poin t. this bit can be used to connect and disconnect external circui ts and components to ground under program control and thereby minimize dc current consumption when the external circuit or component is not being used. this bit is used in conjunctio n with adcmde[6] to select a 20k ? resistor to ground. 6, 5 current channel (32-bit) accumulator enable 0, 0 accumulator disabled and reset to 0 0, 1 accumulator active positive current values are added to accumulator total, accumulator ca n overflow if allowed run for > 65535 conversions negative current values are subtracted from accumulator total, accumulato r is clamped to a minimum value of 0 1, 0 accumulator active positive current values are added to accumulator total, accumulator ca n overflow if allowed run for > 65535 conversions the absolute values of negative current are subtracted from accumulator total, accu mulator in this mode will continue to accumulate negatively, below 0 1, 1 not defined. 4, 3 current channel adc comparator enable 0, 0 comparator disabled 0, 1 comparator active, interrupt asserted if abso lute value of i-adc conversion result |i| >= adc0th 1, 0 comparator-count mode active, interru pt asserted if absolute value of an i-adc conversion result |i| >= adc0th for #adc0tcl conversions. a conversion value |i| < adc0th will reset the threshold counter value (adc0thv) to 0 1, 1 comparator-count mode active, interru pt asserted if absolute value of an i-adc conversion result |i| >= adc0th for #adc0tcl conversions. a conversion value |i| < adc0th will decrement the threshold counter value (adc0thv) towards 0. 2 current channel adc over range enable set by user to enable a coarse comparator on the current cha nnel adc. if the current reading is grossly (>30% approx.) over- ranged for the active gain setting, then the over range bit in th e adcsta mmr is set. the current must be outside this range fo r greater than 125secs for the flag to be set. this feature should not be used in adc low power mode 1 not used this bit is reserved for future function ality and be written as 0 by user code 0 current channel adc, result counter enable set by user to enable the result count mo de. in this mode an i-adc interrupt will only be generated when adc0rcv=adc0rcl. this allows the i-adc to continuously monitor current but only interrupt the mcu core after a defined number of conversions. the voltage/temperature adc will also continue to convert if enab led but again only the last conversion result will be availabl e (intermediate v/t-adc conversion results are not stored) when the adc counter interrupt occurs
aduc7030/aduc7033 preliminary technical data rev. pre | page 62 of 150 current channel adc data register: name: adc0dat address: 0xffff0520 default value: 0x0000 access: read only function: this adc data mmr holds the 16-bit conversion result from the i-adc. the adc will not update this mmr if the adc0 conversion result ready bit (adcsta[0]) is set. a read of this mmr by the mcu clears all asserted ready flags (adcsta[2:0]). voltage channel data register: name: adc1dat address: 0xffff0524 default value: 0x0000 access: read only function: this adc data mmr holds the 16-bit voltage conversion result from the v/t-adc. the adc will not update this mmr if the voltage conversion result ready bit (adcsta[1]) is set. if i-adc is not active, a read of this mmr by the mcu clears all asserted ready flags (adcsta[2:1]). temperature channel adc data register: name: adc2dat address: 0xffff0528 default value: 0x0000 access: read only function: this adc data mmr holds the 16-bit temperature conversion result from the v/t-adc. the adc will not update this mmr if the temperature conversion result ready bit (adcsta[2]) is set. if i-and v adc is not active, a read of this mmr by the mcu clears all asserted ready flags (adcsta[2]). a ready of this mmr will clear adcsta[2]. current channel adc offset calibration register: name: adc0of address: 0xffff0530 default value: part specific, factory programmed access: read/write access function: this adc offset mmr holds a 16-bit offset calibration coefficient for the i-adc. the register is configured at power- on with a factory default value. however, this register will be automatically overwritten if an offset calibration of the i- adc is initiated by the user via bits in the adcmde mmr. user code can only write to this calibration register if the adc is in idle mode. an adc must be enabled and in idle mode before written to any offset or gain register. the adc must be in idle mode for at least 23s.
preliminary technical data aduc7030/aduc7033 rev. pre | page 63 of 150 voltage channel offset calibration register: name: adc1of address: 0xffff0534 default value: part specific, factory programmed access: read/write access function: this offset mmr holds a 16-bit offset calibration coefficien t for the voltage channel. the register is configured at power-on with a factory default value. however, this register will be automa tically overwritten if an offset calibration of the voltage channel is initiated by the user via bits in the adcmde mmr. user code can only write to this calibration register if the adc is in idle mode. an adc must be enabled and in idle mode before written to any offset or gain register. the adc must be in idle mode for at least 23s. temperature channel offset calibration register: name: adc2of address: 0xffff0538 default value: part specific, factory programmed access: read/write function: this adc offset mmr holds a 16-bit offset calibration co efficient for the temperature channel. the register is configured at power-on with a factory default value. howeve r, this register will be automatically overwritten if an offset calibration of the temperature ch annel is initiated by the user via bits in the adcmde mmr. user code can only write to this calibration register if the adc is in id le mode. an adc must be enabled and in idle mode before written to any offset or gain register. the adc must be in idle mode for at least 23s. current channel adc gain calibration register: name: adc0gn address: 0xffff053c default value: part specific, factory programmed access: read/write function: this gain mmr holds a 16-bit gain calibration coefficient for scaling the i-adc conversion result. the register is configured at power-on with a factory default value. however, this register will be automatically overwritten if a gain calibration of the i-adc is initiated by the user via bits in the adcmde mmr. user code can only write to this calibration register if the adc is in idle mode. an adc must be enabled and in idle mode before written to any offset or gain register. the adc must be in idle mode for at least 23s.
aduc7030/aduc7033 preliminary technical data rev. pre | page 64 of 150 voltage channel gain calibration register: name: adc1gn address: 0xffff0540 default value: part specific, factory programmed access: read/write function: this gain mmr holds a 16-bit gain calibration coefficient fo r scaling a voltage channel conversion result. the register is configured at power-on with a factory default value. however, this register will be automatically overwritten if a gain calibration of the voltage channel is initiated by the user via bits in the adcmde mmr. user code can only write to this calibration register if the adc is in idle mode. an adc must be enabled and in idle mode before written to any offset or gain register. the adc must be in idle mode for at least 23s. temperature channel gain calibration register: name: adc2gn address: 0xffff0544 default value: part specific, factory programmed access: read/write function: this gain mmr holds a 16-bit gain calibration coefficien t for scaling a temperature channel conversion result. the register is configured at power-on with a factory default value. however, this register is automatically overwritten if a gain calibration of the temperature channel is initiated by the user via bits in the adcmde mmr. user code can only write to this calibration register if the adc is in idle mode. an adc must be enabled and in idle mode before written to any offset or gain register. the adc must be in idle mode for at least 23s. current channel adc result counter limit register: name: adc0rcl address: 0xffff0548 default value: 0x0001 access: read/write function: this 16-bit mmr sets the number of conversions required before an adc interrupt is generated. by default this register is set to 0x01. the adc counter function must be enabled via the adc result counter enable bit in the adccfg mmr. current channel adc result count register: name: adc0rcv address: 0xffff054c default value: 0x0000 access: read only function: this 16-bit, read only mmr holds the current number of i- adc conversion results. it is used in conjunction with adc0rcl to mask i-adc interrupts, generating a lower interrupt rate. once adc0rcv=adc0rcl, the value is adc0rcv resets to 0 and recommences counting. it can also be used in conjunction with the accumulator (adc0acc) to allow an average current calculation to be undertaken. the result counter is enabled via adccfg[0]. this mmr is also reset to 0 when the i-adc is reconfigured i.e. when the adc0con or adcmde are written.
preliminary technical data aduc7030/aduc7033 rev. pre | page 65 of 150 current channel adc threshold register: name: adc0th address: 0xffff0550 default value: 0x0000 access: read/write function: this 16-bit mmr sets the threshold against which the absolute value of the i-adc conversion result is compared. in unipolar mode adc0th [15:0] are compared and in 2s complement mode adc0th[14:0] are compared. current channel adc threshold count limit register: name: adc0tcl address: 0xffff0554 default value: 0x01 access: read/write function: this 8-bit mmr determines how many cumulative (given values below the threshold will decrement or reset the count to 0) i-adc conversion result readings above adc0th must occur before the i-adc comparator threshold bit is set in the adcsta mmr generating an adc interrupt. the i-adc comparator threshold bit is asserted as soon as the adc0thv=adc0tcl. current channel adc threshold count register: name: adc0thv address: 0xffff0558 default value: 0x00 access: read only function: this 8-bit mmr is incremented every time the absolute value of an i-adc conversion result |i| >= adc0th. this register is decremented or reset to 0 every time the absolu te value of an i-adc conversion result |i| < adc0th. the configuration of this function is enabled via the current channel adc comparator bits in the adccfg mmr. current channel adc accumulator register: name: adc0acc address: 0xffff055c default value: 0x00000000 access: read only function: this 32-bit mmr holds the current accumulator value. the i-adc ready bit in the adcsta mmr should be used to determine when it is safe to read this mmr. the mmr value is reset to 0 by disabling the accumulator in the adccfg mmr or reconfiguring the current channel adc.
aduc7030/aduc7033 preliminary technical data rev. pre | page 66 of 150 low power voltage reference scaling factor name: adcref address: 0xffff057c default value: part specific, factory programmed access: read/write. care should be taken not to write to this register. function: this allows user code to correct for the initial error of the lpm reference. 0x8000 corresponds to no error when compared to the normal mode reference. the magnitude of the adc result should be multiplied by the value in adcref and divided by 0x8000 to compensate for the actual value of the low power reference if the lpm voltage reference is 1% below 1.200v, then the value of adcref will be approximately 0x7eb9 if the lpm voltage reference is 1% above 1.200v, then the value of adcref will be approximately 0x8147 this register corrects the effective value of the lpm reference at the temperature the reference is measured at during adi's pr oduction flow, which is 25c. there is no change to the temperature-coefficient of the lpm reference when using the adcref mmr.. this register should not be used if the precision reference is being used in low power mode (if adcmde[5] is set.) adc power modes of operation the adcs can be configured into various reduced or full power modes of operation by configuring adcmde[4:3] as appropriate. the arm7 mcu can itself also be configured in low power modes of operation (powcon[5:3]). the core power modes are independently controlled and are not related to the adc power modes described here. the adc power modes of operation are described in more detail below. adc startup procedure prior to beginning converting, the following procedure should be followed. 1. configure the current adc, adc0, into low-power- mode (adc0con = 0x8007; adcmde = 0x09) 2. delay for 200s. 3. switch the current adc, adc0, into idle-mode (adcmde = 0x03), keeping adc0con unchanged. if the voltage or temperature channels are to be used, they should be enabled here. 4. delay for 1ms 5. switch adcmde to desired mode, for example. adcmde = 0x1. adc normal power mode in normal mode, the current and voltage/temperature channels are fully enabled. the adc modulator clock is 512khz and enables the adcs to provide regular conversion results at a rate of between 4hz and 8khz (see adcflt). both channels are under full control of the mcu and can be reconfigured at any time. the default adc update rate for all channels in this mode is 1.0khz it is worth emphasizing that i-adc and v/t-adc channels can be configured to initiate periodic, normal power mode, high accuracy, single conversion cycles before returning to adc full power-down mode. this flexibility is facilitated under full mcu control via the adcmde mmr and ensures that continuous periodic monitoring of battery current, voltage and temperature settings is feasible while ensuring the average dc current consumption is minimized. in adc normal mode, the pll must not be powered down. adc low power mode in adc low power mode, the i-adc is enabled in a reduced power and reduced accuracy configuration. the adc modulator clock is now driven directly from the on-chip 131khz low power oscillator, which allows the adc to be configured at update rates as low as 1hz (adcflt). the gain of the adc in this mode is fixed at 128. all of the adc peripheral functions (result counter, digital comparator and accumulator) described earlier in normal power mode can still be enabled in low power mode. typically, in low power mode, the i-adc only, is configured to run at a low update rate, continuously monitoring battery current. the mcu will be in power-down mode and will only be woken up when the i-adc interrupts the mcu. this would happen after the i-adc detects a current conversion beyond a pre-programmed threshold, set-point or a set number of conversions. it is also possible to select either the adc precision voltage reference or the adc low power mode voltage reference via adcmde[5].
preliminary technical data aduc7030/aduc7033 rev. pre | page 67 of 150 adc low power-plus mode in low power-plus mode, the i-adc channel is enabled in a mode almost identical to low-power mode (adcmde[4:3]). however, in this mode, the i-adc gain is fixed at 512 and the adc consumes an additional 200a (approx.) to yield improved noise performance relative to the low-power mode setting. again, all of the adc peripheral functions (result counter, digital comparator and accumulator) described earlier in normal power mode can still be enabled in low power-plus mode. as in low power mode, the i-adc only, is configured to run at a low update rate, continuously monitoring battery current. the mcu will be in power-down mode and will only be woken up when the i-adc interrupts the mcu. this would happen after the i-adc detects a current conversion result beyond a pre- programmed threshold or set-point. it is also possible to select either the adc precision voltage reference or the adc low power mode voltage reference via adcmde[5]. adc comparator and accumulator every i-adc result can also compared to a pre-set threshold level (adc0th) as configured via adccfg[4:3]. an mcu interrupt is generated if the absolute (sign-independent) value of the adc result is greater than the pre-programmed comparator threshold level. an extended function of this comparator function allows user code to configure a threshold counter (adc0thv) which monitors the number of i-adc results that have occurred above or below the pre-set threshold level. again, an adc interrupt is generated once the threshold counter reaches a pre-set value (adc0tcl). finally, a 32-bit accumulator(adc0acc) function can be configured(adccfg[6:5]) allowing the i-adc to add(or subtract) multiple i-adc sample results. user code to read the accumulated value directly(adc0acc) without any further software processing. adc sinc3 digital filter response the overall frequency response on all aduc7030/aduc7033s adcs is dominated by the low pass filter response of the on- chip sinc3 digital filters. the sinc3 filters are used to decimate the adc sigma-delta modulator output data bit-stream to generate a valid 16-bit data result. the digital filter response is identical for all adcs and is configured via the 16-bit adc filter (adcflt) register, which determines the overall throughput rate of the adcs. the noise resolution of the adcs is determined by the programmed adc throughput rate. in the case of the current channel adc, the noise resolution will be determined by throughput rate and selected gain. the overall frequency response and the adc through-put is dominated by the configuration of the sinc3 filter decimation factor (sf) bits (adcflt[6:0]) and the averaging factor (af) bits(adcflt[13:8]). due to limitations on the digital filter internal data-path, there are some limitations on the allowable combinations of sf(sinc3 decimation factor) and af(averaging factor) that can be used to generate a required adc output rate. this restriction limits the minimum adc update in normal power mode to 4hz or 1hz in low power mode. the calculation of the adc throughput rate is detailed in the adcflt bit designations table and the restrictions on allowable combinations of af and sf values are outlined again in table 36. table 36. allowable combinations of sf and af af range sf 0 1 to 7 8-63 0-31 32-63 64-127 by default the adcflt = 0x07 which configures the adcs for a through-put of 1.0khz with all other filtering options (chop, running average, averaging factor and sin3 modify) being disabled. a typical filter response based on this default configuration is shown in figure 19 below. ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 (db) frequency (khz) 05994-019 figure 19. typical digital filter response at fadc=1.0khz (adcflt = 0x0007) an additional sinc3 modify bit (adcflt[7]) is also available in the adcflt register. this bit is set by user code to modify the standard sinc3 frequency response increasing the filter stop- band rejection by 5dbs approx. this is achieved by inserting a second notch (notch2) at fnotch2 = 1.333 x fnotch where fnotch is the location of the 1st notch in the response. there is a slight increase in adc noise if this bit is active. figure 20 shows the modified 1khz filter response when the sinc3 modify bit is active. the new notch is clearly visible at
aduc7030/aduc7033 preliminary technical data rev. pre | page 68 of 150 1.33khz as is the improvement in stop-band rejection when compared to the standard 1khz response above. ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 (db) frequency (khz) 05994-020 figure 20. modifiedsinc3 digital filter response at fadc=1.0khz (adcflt = 0x0087) in adc normal power mode, the maximum adc throughput rate is 8khz which is configured by setting the sf and af bits in the adcflt mmr to 0, with all other filtering options disabled. this results in 0x0000 written to adcflt and a typical 8khz filter response based on these settings is shown below in figure 21. ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k (db) frequency (khz) 05994-021 figure 21. typical digital filter response at fadc=8 khz, (adcflt = 0x0000) a modified version of the 8khz filter response can be configured by setting the running average bit (adcflt[14]). this has the effect of introducing an additional running average by 2 filter on all adc output samples. this further reduces the adc output noise and while maintaining an 8khz adc through-put rate the adc settling time is increased by 1 full conversion period. the modified frequency response for this configuration is shown below in figure 22. ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k (db) frequency (khz) 05994-022 figure 22. typical digital filter response at fadc=8khz, (adcflt = 0x4000) at very low throughput rates, the chop bit in the adcflt register can be enabled to minimize offset errors and more importantly temperature drift in the adc offset error. with chop enabled, there are again 2 primary variables (sinc3 decimation factor and averaging factor) available to allow the user select an optimum filter response trading off filter bandwidth against adc noise. for example, with the chop bit adcflt[15] set to 1, increasing the sf value (adcflt[6:0]) to 0x1f (31dec) and selecting an af value (adcflt[13:8]) of 0x16 (22dec) results in an adc through-put of 10hz. the frequency response in this case is shown in figure 23. ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 200 180 160 140 120 100 80 60 40 20 (db) frequency (khz) 05994-023 figure 23 typical digital filter respon se at fadc=8 khz, (adcflt = 0x961f) changing sf to 0x1d and setting af to 0x3f, again with the chop bit enabled, configures the adc into its minimum through-put rate in normal mode of 4hz. the digital filter frequency response with this configuration is shown below in figure 24.
preliminary technical data aduc7030/aduc7033 rev. pre | page 69 of 150 ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 060 40 20 (db) frequency (khz) 05994-024 figure 24. typical digital filter response at fadc=4hz, (adcflt = 0xbf1d) in adc low power mode, the adc, sigma-delta modulator clock no longer driven at 512khz but is driven directly from the on-chip low power (131khz) oscillator. subsequently, for the same adcflt configurations in normal mode, all filter values should be scaled by a factor of approximately four. this means that it is possible to configure the adc for 1hz throughput in low power mode. the filter frequency response for this configuration is shown below in figure 25. ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 020 18 16 14 12 10 8 6 4 2 (db) frequency (khz) 05994-025 figure 25. typical digital filter response at fadc=1hz, (adcflt = 0xbd1f in general, it should be noted that it is possible to program different values of sf and af in the adcflt register and achieve the same adc update rate. in practical terms, the trade-off with any value of adcflt will be frequency response versus adc noise. for optimum filter response and adc noise when using combinations of sf and af, a good rule of thumb to use would be to first choose an sf in the range of 16 C 40 (dec) or 0x10 to 0x28 and then increase the af value to achieve the required adc through-put. table 37 shows some common adcflt configurations. table 37. common adcflt configurations adc mode sf af other config adcflt fadc tsettle normal 0x1d 0x3f chop on 0xbf1d 4hz 0.5secs normal 0x1f 0x16 chop on 0x961f 10hz 0.2secs normal 0x07 0x00 none 0x0007 1khz 3msecs normal 0x07 0x00 sinc 3 modifiy 0x0087 1khz 3msec normal 0x03 0x00 running average 0x4003 2khz 2msec normal 0x00 0x00 running average 0x4000 8khz 0.5ms low power 0x10 0x03 chop on 0x8310 20hz 100ms low power 0x10 0x09 chop on 0x8910 10hz 200ms low power 0x1f 0x3d chop on 0xbd1f 1hz 2sec adc calibration as described in detail in the top-level diagrams at the start of this section, the signal flow through all adc channels can be described in simple terms as: an input-voltage is applied through an input buffer (and pga in the case of the i-adc) to the sigma-delta modulator. the modulator-output is applied to a programmable digital decimation filter. the filter output result is then averaged if chopping is used. an offset value (adcxof) is subtracted from the result. this result is scaled by a gain value (adcxgn). finally, the result is formatted as - 2s complement. / offset-binary, - rounded to 16 bits - clamped to +/-full-scale each adc has a specific offset and gain correction or calibration coefficient associated with it that are stored in mmr based offset and gain registers(adcxof and adcxgn). the offset and gain registers can be used to remove offsets and gain errors arising within the part as well as system- level offset and gain errors external to the part. these registers are configured at power-on with a factory programmed calibration value. these factory calibration values will vary from part to part reflecting the manufacturing variability of internal adc circuits. however, these registers can also be overwritten by user code (only if the adc is in idle mode) and will be automatically overwritten if an offset or gain
aduc7030/aduc7033 preliminary technical data rev. pre | page 70 of 150 calibration cycle is initiated by user via the mode bits in the adcmde[2:0] mmr. 2 types of automatic calibration are available to the user, namely: self (offset or gain) calibration, where the adc generates its calibration coefficient based on an internally generated 0v in the case of self-offset calibration and full-scale voltage in the case of self-gain calibration. it should be emphasized that adc self-calibrations correct for offset and gain errors within the adc. self-calibrations cannot compensate for other external errors in the system, e.g. shunt-resistor tolerance/drift, external offset voltages etc. system (offset or gain) calibration, where the adc generates its calibration coefficient based on an externally generated zero- scale voltage in the case of system-offset calibration and full- scale voltage in the case of system-gain calibration, which are applied to the external adc input for the duration of the calibration cycle. the duration of an offset calibration is 1 single conversion cycle (3/fadc chop off, 2/fadc chop on) before returning the adc to idle mode. a gain calibration is a 2-stage process and subsequently takes twice as long as an offset calibration cycle. once a calibration cycle is initiated, any ongoing adc conversion is immediately halted, the calibration is carried out automatically at an adc update rate programmed into adcflt and the adc is always returned to idle after any calibration cycle. it is strongly recommended that adc calibration is initiated at as low an adc update rate as possible (high sf value in adcflt) in order to minimize the impact of adc noise during calibration. note: in self-calibration mode, adc0gn must first contain the values for pga = 1 before a calibration scheme is started using the offset and gain calibration if the chop bit (adcflt[15]) is enabled, then internal adc offset errors will be minimized and an offset calibration may not be required. if chopping is disabled however, an initial offset calibration will be required and may need to be repeated particularly after a large change in temperature. a gain calibration, particularly in the context of the i-adc (with internal pga) may need to be carried out at all relevant system gain ranges depending on system accuracy requirements. if it is not possible to apply an external full-scale current on all gain ranges then it is possible to apply a lower current, and scale the result produced by the calibration. e.g apply a 50% current and then divide the adc0gn value produced by 2 and write this value back into adc0gn. it should be noted that there is a lower limit to the input signal that can be applied for a system-calibration because the adc0gn register is only 16-bit. the input span (difference between the system zero-scale value and system full-scale value) should be greater than 40% of the nominal full-scale- input range, that is, > 40% of v ref /gain. the on-chip flash/ee memory can be used to store multiple calibration coefficients, which can be copied by user code directly into the relevant calibration registers as appropriate based on system configuration. in general, the simplest way to use the calibration registers is to let the adc calculate the values required as part of the adc automatic calibration modes. a factory or end-of-line calibration for the i-adc would be a 2-step procedure: 1. apply 0a current. configure the adc in the required pga setting etc. and write to adcmde[2:0] to perform a system zero-scale calibration. this writes a new offset calibration value into adc0of. 2. apply a full-scale current for the selected pga setting. write to adcmde to perform a system full-scale calibration. this writes a new gain calibration value into adc0gn. understanding the offset and gain calibration registers the output of the average block in the adc signal flow described earlier after the digital filter and before the offset and gain scaling can be considered to be a fractional number with a span, for a +/- full-scale input, of approx +/-0.75. the span is less than +/-1.0 because there is attenuation in the modulator to accommodate some over-range capacity on the input signal. the exact value of the attenuation will vary slightly from part- to-part, because of manufacturing tolerances. the offset coefficient is read from the adc0of calibration register. this value is a 16-bit 2's complement number. the range of this number, in terms of the signal chain, is effectively +/-1.0. 1 lsb of the adc0of register is therefore not the same as 1lsb of adc0dat. a positive value of adc0of indicates that offset is subtracted from the output of the filter, a negative value is added. the nominal value of this register is 0x0000, indicating zero offset is to be removed. the actual offset of the adc may vary slightly from part-to-part and at different pga gains. the offset within the adc is minimized if the chopping mode is active (adcflt[15]=1). the gain coefficient is a unit less scaling factor. the 16-bit value in this register is divided by 16384, and then multiplied by the offset-corrected value. the nominal value of this register equals 0x5555, which corresponds to a multiplication factor of 1.3333. this scales the nominal +/-0.75 signal to produce a full- scale output signal of +/-1.0 which is checked for overflow/ underflow and converted to two's complement or unipolar mode as appropriate, before being output to the data register. the actual gain, and the required scaling coefficient for zero gain error, varies slightly from part to part, and at different pga settings and in normal / low-power-mode. the value
preliminary technical data aduc7030/aduc7033 rev. pre | page 71 of 150 downloaded into adc0gn at power-on/reset represents the scaling factor for a pga gain=1. there will be some level of gain error if this value is used at different pga settings. user code can over-write the calibration coefficients or run adc calibrations to correct the gain error at the current pga setting. in summary, the simplified adc transfer function can be described as: adcgnnom adcgn adcof vref pga vin adcout * * ? ? ? ? ? ? ? = this equation is valid for voltage/temperature channel adc. for the current channel adc, adcgnnom adcgn adcof k vref pga vin adcout * * * ? ? ? ? ? ? ? = where k is dependent on pga gain setting and adc mode. normal mode: for pga gains of 1,4,8,16,32 and 64 the k factor is 1. for pga gains of 2 and 128 the k factor is 2. for pga gain of 256 the k factor is 4. for pga gain of 512, the k factor is 8. low power mode: the pga gain is set to 128 and the k factor is 32. low power plus mode: the pga gain is set to 512 and the k factor is 8. in low-power and low-power-plus mode, the k factor doubles if (reg_avdd)/2 is used as the reference. adc diagnostics the aduc7030/aduc7033 features diagnostic capability on both adcs. current adc diagnostics the aduc7030/aduc7033 features the capability to detect open circuit conditions on the application board. this is accomplished using the two current sources on iin+ and iin-, which is controlled via adc0con[14,13]. note: these current sources have a tolerance of +-30%. a pga gain equal to or greater than 2 (adc0con [3-0 ] 0001) must be used when current sources are enabled. voltage/temperature adc diagnostics the aduc7030/aduc7033 features the capability to detect open circuit conditions on the voltage/temperature channel inputs. this is accomplished using the two current sources on vtemp+ and gnd_sw, which is controlled via adc1con[14,13]. these functions are described in details in the application note adc diagnostic on the aduc703x series .
aduc7030/aduc7033 preliminary technical data rev. pre | page 72 of 150 power supply support circuits the aduc7030/aduc7033 incorporates an on-chip low drop-out (ldo) regulator, which is driven directly from the battery voltage to generate a 2.6v internal supply. this 2.6v supply is then used as the supply voltage for the arm7 mcu and peripherals including the precision analog circuits on-chip. power on reset (por), power supply monitor (psm) and low voltage flag (lvf) functions are also integrated to ensure safe operation of the mcu as well as continuously monitoring the battery power supply. the por circuit is designed to handle all battery ramp rates and guarantee full functional operation of the flash/ee memory based mcu during power-on and power-down cycles. as shown in figure 26, once the supply voltage, vdd, reaches a minimum operating voltage of 3v, a por signal keeps the arm core in reset for 20ms. this ensures that the regulated power supply voltage. reg_dvdd, supplied to the arm core and associated peripherals is above the minimum operational voltage to guarantee full functionality. a por flag is set in the rststa mmr to indicate a por reset event has occurred. the aduc7030/aduc7033 also features a psm, or power supply monitor function. once enabled via hvcfg0[3], the psm continuously monitors the voltage at the vdd pin. if this voltage drops below 6.0v typically, the psm flag is automatically asserted and can, if the high voltage irq is enabled via irq/fiqen[16], generate a system interrupt. an example of this operation is shown in figure 26. at voltages below the por level, an additional low voltage flag can be enabled (hvcfg0[2]). it can be used to indicate that the contents of the sram are still valid after a reset event. the operation of the low voltage flag is shown in figure 26. once enabled, the status of this bit may be monitored via hvmon[3]. if this bit is set, then the sram contents are valid. if this bit is cleared, then the sram contents may have been corrupted. vdd 12 v 3v typ 2.6v 20ms typ psm trip 6.0v typ por trip 3.0v typ lvf trip 2.1v typ reg_dv dd por_trip reset_core (internal signal) enable_psm enable_lvf 05994-026 figure 26. typical power-on cycle
preliminary technical data aduc7030/aduc7033 rev. pre | page 73 of 150 aduc7030/aduc7033 system clocks the aduc7030/aduc7033 integrates a highly flexible clocking system, which may be clocked from one of three sources: - an integrated on-chip precision oscillator - an integrated on-chip low power oscillator - an external watch crystal these three options are shown in figure 27. each of the internal oscillators are divided by 4 to generate a clock frequency of 32.768khz. the pll locks onto a multiple (625) of 32.768khz, supplied by either of the internal oscillators or the external crystal, to provide a stable 20.48mhz clock for the system. the core can operate at this frequency, or at binary submultiples of it, which allows power saving if peak performance is not required. by default, the pll is driven by the low power oscillator which generates a 20.48mhz clock source. the arm7tdmi core, is driven by a cd divided clock derived from the output of the pll. by default, the cd divider is configured to divide the pll output by 2, which generates a core clock of 10.24mhz. the divide factor may be modified to generate a binary weighted divider factor from 1 to 128, which may be altered dynamically by user code. the adc is driven by the output of the pll, divided to give an adc clock source of 512khz. in low-power mode the adc clock source is switched from the standard 512khz to the low power 131khz oscillator. it should also be noted that the low power oscillator drives both the watchdog and core wake-up timers through a divide by 4 circuit. a detailed block diagram of the aduc7030/aduc7033 clocking system is shown in figure 27. 0 5994-027 spi core clock pll output (20.48mhz) uart core clock precision 131khz div 4 precision oscillator low power oscillator external 32.768khz low power 131khz div 4 pllcon pll flash controller eclk 2.5mhz precision 32.768khz low power 32.768khz pll output 20.48mhz crystal circuitry external crystal (optional) pll lock 1 8 adcmde clock divider core clock 1 2 cd mcu adc clock adc high accurcy calibration counter external 32.768khz precision 131khz low power calibration counter low power oscillator timer 0 life time core clock external 32.768khz precision 32.768khz low power 32.768khz gpio_5 timer 1 core clock gpio_8 low power 32.768khz timer 2 wake-up core clock low power 32.768khz precision 32.768khz external 32.768khz watchdog timer 3 low power 32.768khz timer 4 sti low power 32.768khz core clock lin h/w synchronization low power 32.768khz pll output (5mhz) figure 27. aduc7030/aduc7033 system clock generation
aduc7030/aduc7033 preliminary technical data rev. pre | page 74 of 150 the operating mode, clocking mode and programmable clock divider are controlled via two mmrs, pllcon and powcon, and the status of the pll is indicated by pllsta. pllcon controls the operating mode of the clock system while powcon controls the core clock frequency and the power- down mode. pllsta indicates the presence of an oscillator on the xtal1 pin, the pll lock status, and the pll interrupt. it is recommended that before the aduc7030/aduc7033 is powered down, that the clock source for the pll is switched to the low power 131khz oscillator to reduce wake up time. the low power oscillator is always active. when the aduc7030/aduc7033 wakes up from power down, the mcu core will begin executing code once the pll begins oscillating. this occurs before the pll has locked to a frequency of 20.48mhz. to ensure the flash/ee memory controller is executing with a valid clock, the controller is driven with a pll-output/8 clock source while the pll is locking. once the pll locks, the plls output is switched from the pll-output/8 to the locked pll-output. if user code requires an accurate pll output, user code must poll the lock bit (pllsta[1]) after wake-up before resuming normal code execution. the pll will be locked within 2ms, if the pll is clocked from an active clock source, e.g. low power 131khz oscillator after waking up. pllcon is a protected mmr with two 32-bit keys pllkey0, a pre write key, and pllkey1, a post write key. pllkey0 = 0x000000aa pllkey1 = 0x00000055 powcon is a protected mmr with two 32-bit keys powkey0, a pre write key, and powkey1, a post write key. powkey0 = 0x00000001 powkey1 = 0x000000f4 an example of writing to both mmrs is shown below: powkey0 = 0x01 //powcon key powcon = 0x00 //full power-down powkey1 = 0xf4 //powcon key ia1*ia2 //dummy cycle to clear the pipe line, where ia1 and ia2 are defined as longs and are not 0 pllkey0 = 0xaa //pllcon key pllcon = 0x0 //switch to lp osc. pllkey1 = 0x55 //pllcon key ia1*ia2 //dummy cycle to prevent flash/ee access during clock change pllsta register: name: pllsta address: 0xffff0400 default value: access: read only function: this 8-bit register allows user code to monitor the lock state of the pll and the status of the external crystal. table 38. pllsta mmr bit description bit description 31 to 3 reserved 2 xtal clock, read only this is a live representation of the current logic level on xtal1. this allows the user to check to see if an external clock so urce is present. if present, this bit will alternat e high and low at a frequency of 32.768khz. 1 pll lock status bit, read only set when the pll is locked and outputting 20.48mhz. clear when the pll is not locked and outputting a fcore/8 clock source 0 pll interrupt: set if the pll lock status bit signal goes low. cleared by writing 1 to this bit
preliminary technical data aduc7030/aduc7033 rev. pre | page 75 of 150 pllcon pre-write key pllkey0: name: pllkey0 address: 0xffff0410 access: wr ite only key: 0x000000aa function: pllcon is a keyed register that requires a 32-bit key value to be written before and after pllcon. pllkey0 is the pre-write key. pllcon pre-write key pllkey1: name: pllkey1 address: 0xffff0418 access: wr ite only key: 0x00000055 function: pllcon is a keyed register that requires a 32-bit key value to be written before and after pllcon. pllkey1 is the post-write key. pllcon register: name: pllcon address: 0xffff0414 default value: 0x00 access: read/write function: this 8-bit register allows user code dynamically select the pll source clock from three different oscillator sources. table 39. pllcon mmr bit description bit description 31-2 reserved, these bits should be written as 0 by user code pll clock source 1 00 low power 131khz oscillator 01 precision 131khz oscillator 2 10 external 32.768khz crystal 1-0 11 reserved 1 if user code switches mcu clock sources, a dummy mcu cycle should be included after the clock switch is written to pllcon 2 powcon[7] must be enabled prior to switching to this clock source powcon pre-write key powkey0: name: powkey0 address: 0xffff0404 access: wr ite only key: 0x00000001 function: powcon is a keyed register that requires a 32- bit key value to be written before and after powcon. powkey0 is the pre-write key. powcon pre-write key powkey1: name: powkey1 address: 0xffff040c access: wr ite only key: 0x000000f4 function: powcon is a keyed register that requires a 32- bit key value to be written before and after powcon. powkey1 is the post-write key.
aduc7030/aduc7033 preliminary technical data rev. pre | page 76 of 150 powcon register: name: powcon address: 0xffff0408 default value: 0x079 access: read/write function: this 8-bit register allows user code dynamically enter various low power modes and modify the cd divider which controls the speed of the arm7tdmi core. table 40. powcon mmr bit designations bit description 31-8 reserved 7 precision 131khz input enable: cleared by the user to power down the precision 131khz input enable. set by the user to enable the precisio n 131khz input enable. the precision 131khz oscillator must also be enabled via hvcfg0[6]. setting this bit increases curre nt consumption by approximately 50ua and should be disabled when not in use. 6 xtal power down: cleared by the user to power down the external crystal circuitry. set by the user to enable the external crystal circuitry. 5 pll power down 1 : this bit is cleared to 0 to pow er down the pll. the pll can not be powered down if either the core or peripherals are enabled: bits 3, 4 and 5 must be cleared simultaneously. set by default, and set by hardware on a wake up event 4 peripherals 2,3, 4 power down: cleared to power down the peripherals. the peripherals cannot be powered down if the core is en abled: bits 3 and 4 must be cleared simultaneously. set by default, or and by hardware on a wake up event 3 core power down: 5 cleared to power down the arm core set by default, and set by hardware on a wake up event cd core clock divider bits: 000 20.48 mhz 48.83ns 001 10.24 mhz 97.66ns 010 5.12 mhz 195.31ns 011 2.56 mhz 390.63ns 100 1.28 mhz 781.25ns 101 640 khz 1.56s 110 320 khz 3.125s 2-0 111 160 khz 6.25s 1 timer peripherals will be powered down if driven from the pll output clock. timers driven from an active clock source will sta y in normal power mode. 2 the peripherals that are powered down by this bit are as follows: sram, flash/ee memory and gpio interfaces spi and uart serial ports 3 lin can still respond to wake-up events even if this bit is cleared. 4 wake-up timer (timer2) can still be active if driven from low power oscillator even if this bit is set. 5 if user code powers down the mcu, a du mmy mcu cycle should be included after the power-down command is written to powcon.
preliminary technical data aduc7030/aduc7033 rev. pre | page 77 of 150 aduc7030/ aduc7033 low power clock calibration the low power 131 khz oscillator may be calibrated using either the precision 131khz oscillator, or an external 32.768 khz watch crystal. two dedicated calibration counters and an oscillator trim register are used to implement this feature. one counter, 9-bits wide, is clocked by the accurate clock oscillator, either the precision oscillator or external watch crystal. the second counter, 10-bits wide, is clocked by the low power oscillator, either directly at 131khz or via a divide by 4 block generating 32.768khz. the source for each calibration counter should be of the same frequency. the trim register (osc0trm) is an 8-bit wide register, the lower 4-bits of which are user accessible trim bits. increasing the value in osc0trm will decrease the frequency of the low power oscillator, decreasing the value will increase the frequency. based on a nominal frequency of 131khz, the typical trim range is between 127khz to 135khz. the clock calibration mode is configured and controlled by the following mmrs: osc0con: control bits for calibration. osc0sta: calibration status register osc0val0: 9-bit counter. counter 0. osc0val1: 10-bit counter. counter 1. osc0trm: oscillator trim register. an example calibration routine is shown in figure 28. user code configures and enables the calibration sequence via osc0con. when the precision oscillator calibration counter, osc0val0, reaches 0x1ff, both counters are disabled. user code then reads back the value of the low power oscillator calibration counter. there are three possible scenarios: osc0val0 = osc0val1. no further action is required. osc0val0 > osc0val1. the low power oscillator is running slow. osc0trm must be decreased. osc0val0 < osc0val1. the low power oscillator is running fast. osc0trm must be increased. when the osc0trm has been changed the routine should be re-run and the new frequency checked. using the internal precision 131khz oscillator, it will take approximately 4milliseconds to execute the calibration routine. if the external 32.768khz crystal is used, this time increases to 16milliseconds. note: prior to the clock calibration routine been started, it is required that the user switch to either the precision 131khz oscillator or the external 32.768khz watch crystal as the pll clock source. if this is not done, it is possible that the pll will lose lock each time osc0trm is modified. this will increase the length of time it takes to calibrate the low power, oscillator. 05994-028 begin calibration routine while oscsta[0] = 1 increase osc0trm decrease osc0trm osc0val0 < osc0val1 osc0val0 > osc0val1 end calibration routine is error within desired level? osc0val0 = osc0val1 no yes figure 28. example osc0 trm calibration routine
aduc7030/aduc7033 preliminary technical data rev. pre | page 78 of 150 osc0trm register: name: osc0trm address: 0xffff042c default value: 0xx8 access: read/write function: this 8-bit register controls the low power oscillator trim table 41. osctrm mmr bit definition bit description 7 to 4 reserved and should be written as zeros 3 to 0 user trim bits osc0con register: name: osc0con address: 0xffff0440 default value: 0x00 access: read/write function: this 8-bit register controls the low power oscillator calibration routine table 42. osccon mmr bit definition bit description 7-5 reserved. should be written as 0 4 calibration source set to select external 32.768khz crystal cleared to select internal precision 131khz oscillator. 3 calibration reset set to reset the calibration counters and disable the calibration logic 2 set to clear oscval1 1 set to clear oscval0 0 calibration enable set to begin calibration cleared to abort calibration
preliminary technical data aduc7030/aduc7033 rev. pre | page 79 of 150 osc0sta register: name: osc0sta address: 0xffff0444 default value: 0x00 access: read access only function: this 8-bit register gives the status of the low power oscillator calibration routine table 43. oscsta mmr bit definition bit description 7-2 reserved 1 calibration complete set by hardware on full completion of a calibration cycle cleared by a read of osc1val1 0 set if calibration is in progress. cleared if calibration completed osc0val0 register: name: osc0val0 address: 0xffff0448 default va lu e: 0x00 access: read access only function: this 9-bit counter is clocked from either the 131khz precision oscillator or the 32.768khz external crystal. osc0val1 register: name: osc0val1 address: 0xffff044c default va lu e: 0x00 access: read access only function: this 10-bit counter is clocked from the low power, 131khz oscillator.
aduc7030/aduc7033 preliminary technical data rev. pre | page 80 of 150 processor reference peripherals interrupt system there are 16 interrupt sources on the aduc7030/aduc7033, which are controlled by the interrupt controller. most interrupts are generated from the on-chip peripherals such as the adc, uart, etc.. the arm7tdmi cpu core will only recognize interrupts as one of two types, a normal interrupt request irq and a fast interrupt request fiq. all the interrupts can be masked separately. the control and configuration of the interrupt system is managed through nine interrupt-related registers, four dedicated to irq, four dedicated to fiq. an additional mmr is used to select the programmed interrupt source. the bits in each irq and fiq registers represent the same interrupt source as described in table 44. irqsta/fiqsta should be saved immediately upon entering the isr (interrupt service routine) to ensure that all valid interrupt sources are serviced. the interrupt generation route through the arm7tdmi core is shown in figure 29. consider the example of timer0, which is configured to generate a timeout every 1ms. after the first 1ms timeout, fiqsig/irqsig[2] will be set and will only be cleared by writing to t0clri. if timer0 is not enabled in either irqen or fiqen, then fiqsta/irqsta[2] will not be set and an interrupt will not occur. if timer0 is enabled in either irqen or fiqen, then either fiqsta/irqsta[2] will be set and either an fiq or an irq interrupt will occur. please note that the irq and fiq interrupt bit definitions in the cpsr only control interrupt recognition by the arm core, not by the peripherals. for example, if timer2 is configured to generate an irq via irqen, the irq interrupt bit is set (disabled) in the cpsr and the aduc7030 is powered down. when an interrupt occurs, the peripherals will be woken, but the arm core will remain powered down. this is equivalent to powcon = 0x71. the arm core can only be powered up by a reset event if this occurs. table 44. irq/fiq mmrs bit description bit description for more information please refer to: 0 all interrupts ored 1 swi: not used in irqen/clr and fiqen/clr 2 timer 0 timer0life-time timer 3 timer 1 timer1 4 timer 2 - wake up timer timer2 - wake-up timer 5 timer 3 - watchdog timer timer3 - watchdog timer 6 timer 4 - sti timer timer4 - sti timer 7 lin hardware lin (local interconnect network) interface 8 flash/ee interrupt aduc7030 flash/ee control interface 9 pll lock aduc7030/aduc7033 system clocks 10 adc 16-bit ?? analog to digital converters 11 uart uart serial interface 12 spi serial peripheral interface 13 xirq0 ( gpio irq 0 ) 14 xirq1 ( gpio irq 1 ) 15 reserved 16 irq3 high voltage irq high voltage interrupt 17 reserved 18 xirq4 ( gpio irq 4 ) 19 xirq5 ( gpio irq 5 )
preliminary technical data aduc7030/aduc7033 rev. pre | page 81 of 150 irq the irq is the exception signal to enter the irq mode of the processor. it is used to service general purpose interrupt handling of internal and external events. the four 32-bit registers dedicated to irq are: irqsig, reflects the status of the different irq sources. if a peripheral generates an irq signal, the corresponding bit in the irqsig will be set, otherwise it is cleared. the irqsig bits are cleared when the interrupt in the particular peripheral is cleared. all irq sources can be masked in the irqen mmr. irqsig is read-only. irqen, provides the value of the current enable mask. when bit is set to 1, the source request is enabled to create an irq exception. when bit is set to 0, the source request is disabled or masked which will not create an irq exception. irqen register cannot be used to disable an interrupt. irqclr, (write-only register) allows clearing the irqen register in order to mask an interrupt source. each bit set to 1 will clear the corresponding bit in the irqen register without affecting the remaining bits. the pair of registers irqen and irqclr allows independent manipulation of the enable mask without requiring an atomic read-modify-write. irqsta, (read-only register) provides the current enabled irq source status (effectively a logic and of the irqsig and irqen bits). when set to 1 that source will generate an active irq request to the arm7tdmi core. there is no priority encoder or interrupt vector generation. this function is implemented in software in a common interrupt handler routine. all 32 bits are logically ored to create a single irq signal to the arm7tdmi core. fiq the fiq (fast interrupt request) is the exception signal to enter the fiq mode of the processor. it is provided to service data transfer or communication channel tasks with low latency. the fiq interface is identical to the irq interface providing the second level interrupt (highest priority). four 32-bit registers are dedicated to fiq, fiqsig, fiqen, fiqclr and fiqsta. bit 31 to 1 of fiqsta are logically ored to create the fiq signal to the core and the bit 0 of both the fiq and irq registers (fiq source). the logic for fiqen and fiqclr will not allow an interrupt source to be enabled in both irq and fiq masks. a bit set to 1 in fiqen will, as a side effect, clear the same bit in irqen. a bit set to 1 in irqen will, as a side effect, clear the same bit in fiqen. an interrupt source can be disabled in both irqen and fiqen masks. programmed interrupts as the programmed interrupts are non-maskable, they are controlled by another register, swicfg, which write into both irqsta and irqsig register s or/and fiqsta and fiqsig registers at the same time. the 32-bit register dedicated to software interrupt is swicfg described in table 45. this mmr allows the control of programmed source interrupt. table 45. swicfg mmr bit descriptions bit description 31-3 reserved 2 programmed interrupt-fiq setting/clearing this bit correspond in setting/clearing bit 1 of fiqsta and fiqsig 1 programmed interrupt-irq setting/clearing this bit correspond in setting/clearing bit 1 of irqsta and irqsig 0 reserved note that any interrupt signal must be active for at least the minimum interrupt latency time, to be detected by the interrupt controller and to be detected by user in the irqsta/fiqsta register. 05994-029 irqsta fiqsta irqsig fiqsig timer0 timer1 timer2 timer3 lin h/w flash/ee pll lock adc uart spi xirq irqen fiqen timer0 timer1 timer2 timer3 lin h/w flash/ee pll lock adc uart spi xirq irq fiq figure 29. interrupt structure
aduc7030/aduc7033 preliminary technical data rev. pre | page 82 of 150 timers the aduc7030/aduc7033 features five general purpose timer/counters: - timer0, or life-time timer - timer1, - timer2 or wake-up timer, - timer3 or watchdog timer. - timer4 or sti timer. the five timers in their normal mode of operation may either be free-running or periodic. in free-running mode, the counter decrements/increments from the maximum/minimum value until zero/full scale and starts again at the maximum /minimum value. in periodic mode the counter decrements/increments from the value in the load register(txld mmr,) until zero/full scale and starts again at the value stored in the load register. note that the txld mmr should be configured before the txcon mmr. the value of a counter can be read at any time by accessing its value register (txval). timers are started by writing in the control register of the corresponding timer (txcon). in normal mode, an irq is generated each time the value of the counter reaches zero, if counting down, or full-scale, if counting up. an irq can be cleared by writing any value to clear register of the particular timer (txclri). table 46. timer event capture bit description 0 timer 0 C life time timer 1 timer 1 2 timer 2 - wake up timer 3 timer 3 - watchdog timer 4 timer 4 - sti timer 5 lin hardware 6 flash/ee interrupt 7 pll lock 8 adc 9 uart 10 spi 11 xirq0 - ( gpio_0 ) 12 xirq1 - ( gpio_5) 13 reserved 14 irq3 high voltage interrupt 15 reserved 16 xirq4 -( gpio_7) 17 xirq5 - ( gpio_8)
preliminary technical data aduc7030/aduc7033 rev. pre | page 83 of 150 timer0life-time timer timer0 is a general purpose 48-bit count-up, or a 16-bit count up/down timer with a programmabl e prescalar. timer0 may be clocked from either the core clock or the low power 32.768khz oscillator, with a prescalar of 1, 16, 256 or 32768. this gives a minimum resolution of 48.83ns when the core is operating at 20.48mhz, and with a prescalar of 1. in 48-bit mode, timer0 counts up from zero. the current c o u nt e r v a l u e m ay b e r e a d f r o m t 0 va l 0 a n d t 0 va l 1 . in 16-bit mode,timer0 may count up or count down. a 16-bit value may be written to t0ld, which will be loaded into the counter. the current counter value may be read from t0val0. timer0 has a capture register (t0cap), which may be triggered by a selected irqs source initial assertion. once triggered, the current timer value is copied to t0cap, and the timer keeps running. this feature can be used to determine the assertion of an event with more accuracy than by servicing an interrupt alone. timer0 reloads the value from t0ld either when timer0 overflows, or immediately when t0clri is written. timer0 interface consists of six mmrs: - t0ld is a 16-bit register, which holds the 16-bit value that is loaded into the counter. t0ld is only available in 16-bit mode. - t0cap is a 16-bit register, which holds the 16-bit value captured by an enabled irq event. t0cap is only available in 16-bit mode. - t0val0/t0val1 are 16-bit and 32-bit registers which hold the 16 least significant bits and 32 most significant bits respectively. t0val0 and t0val1 is read-only. in 16-bit mode, 16-bit t0val0 is used. in 48-bit mode, both 16-bit t0val0 and 32-bit t0val1 are used. - t0clri is an 8-bit register. writing any value to this register will clear the interrupt. t0clri is only available in 16-bit mode. - t0con is the configuration mmr described in table 47. 05994-030 timer0 value low power 32.768khz oscillator precision 32.768khz oscillator external 32.768khz watch crystal core clock frequency prescaler 1, 16, 256, or 32768 timer0 ir q 48-bit up counter 16-bit up/down counter 16-bit load capture irq[31:0] figure 30. timer 0 block diagram timer0 value register: name: t0val0/t0val1 address: 0xffff0304, 0xffff0308 default va lu e: 0x0000, 0x00000000 access: read access only function: t0val0 and t0val1 are 16-bit and 32-bit registers, which hold the 16 least significant bits and 32 most significant bits respectively. t0val0 and t0val1 is read-only. in 16-bit mode, 16-bit t0val0 is used. in 48-bit mode, both 16-bit t0val0 and 32-bit t0val1 are used. timer0 capture register: name: t0cap address: 0xffff0314 default va lu e: 0x0000 access: read access only function: this is a 16-bit register, which holds the 16-bit value captured by an enabled irq event. only available in 16-bit mode.
aduc7030/aduc7033 preliminary technical data rev. pre | page 84 of 150 timer0 control register: name: t0con address: 0xffff030c default value: 0x00000000 access: read/write function: the 32-bit mmr configures the mode of operation of timer0 table 47. t0con mmr bit descriptions bit description 31-18 reserved 17 event select bit: set by user to enable time capture of an event cleared by user to disable time capture of an event 16-12 event select range, 0 to 31: the events are as described in table 46. timer event capture. 11 reserved clock select: 00 core clock ( default ) 01 low power 32.768khz oscillator 10 external 32.768khz watch crystal 10-9 11 precision 32.768khz oscillator 8 count up: ( only available in 16bit mode ) set by user for timer 0 to count up cleared by user for timer 0 to count down (default) 7 timer0 enable bit: set by user to enable timer 0 cleared by user to di sable timer 0 (default) 6 timer 0 mode: set by user to operate in periodic mode cleared by user to operate in free-running mode (default) 5 reserved timer0 mode of operation: 0 16 bit operation ( default ) 4 1 48 bit operation prescalar: 0000 source clock / 1 ( default ) 0100 source clock / 16 1000 source clock / 256 3-0 1111 source clock / 32768
preliminary technical data aduc7030/aduc7033 rev. pre | page 85 of 150 timer0 load registers: name: t0ld address: 0xffff0300 default va lu e: 0x0000 access: read/write function: t0ld0 is a 16-bit register, which holds the 16 bit value that is loaded into the counter. only available in 16-bit mode. timer0 clear register: name: t0clri address: 0xffff0310 access: wr ite only function: this 16-bit, write-only mmr is written (with any value) by user code to refresh(reload) timer0.
aduc7030/aduc7033 preliminary technical data rev. pre | page 86 of 150 timer1 timer1 is a 32-bit general purpose timer, count-down or count- up, with a programmable pre-scalar. the pre-scalar source can be the low power 32.768khz oscillator, the core clock, or from one of two external gpio. this source can be scaled by a factor of 1, 16, 256 or 32768. this gives a minimum resolution of 48.83ns when operating at cd zero, the core is operating at 20.48mhz, and with a pre-scalar of 1 (ignoring external gpio). the counter can be formatted as a standard 32-bit value or as hours:minutes:seconds:hundreths. timer1 has a capture register (t1cap), which can be triggered by a selected irqs source initia l assertion. once triggered, the current timer value is copied to t1cap, and the timer keeps running. this feature can be used to determine the assertion of an event with increased accuracy. timer1 interface consists of five mmrs: - t1ld, t1val and t1cap are 32-bit registers and hold 32-bit unsigned integers. t1val and t1cap are read-only. - t1clri is an 8-bit register. writing any value to this register will clear the timer1 interrupt. - t1con is the configuration mmr described in below. timer1 features a post-scalar. this allows the user to count between1 and 256 the number of timer1 timeouts. to activate the post-scalar, the user sets bit 18 and writes the desired number to count into bits 24-31 of t1con. once that number of timeouts has reached, timer1 may generate an interrupt if t1con[18] is set. note: if the part is in a low power mode, and timer1 is clocked from the gpio or low power oscillator source then, timer1 will continue to operate. timer1 reloads the value from t1ld either when timer1 overflows, or immediately when t1clri is written. timer1 load registers: name: t1ld address: 0xffff0320 default va lu e: 0x00000000 access: read/write function: t1ld is a 32-bit register, which holds the 32-bit value that is loaded into the counter. timer1 clear register: name: t1clri address: 0xffff032c access: wr ite only function: this 32-bit, write-only mmr is written (with any value) by user code to refresh (reload) timer1. timer1 value register: name: t1val address: 0xffff0324 default va lu e: 0xffffffff access: read only function: t1val is a 32-bit register, which holds the current value of timer1. 05994-031 timer1 value low power 3 2.768khz oscillator core clock frequency gpio gpio prescaler 1, 16, 256, or 32768 timer1 irq 32-bit up/down counter 8-bit postscaler 32-bit load capture irq[31:0] figure 31. timer 1 block diagram
preliminary technical data aduc7030/aduc7033 rev. pre | page 87 of 150 timer1 capture register: name: t1cap address: 0xffff0330 default va lu e: 0x00000000 access: read only function: this is a 32-bit register, which holds the 32-bit value captured by an enabled irq event. timer1 control register: name: t1con address: 0xffff0328 default va lu e: 0x01000000 access: read/write function: this 32-bit mmr configures the mode of operation of timer1. table 48. t1con mmr bit descriptions bit description 31-24 8 bit post-scalar by writing to these 8 bits, a value is written to the post-scalar. writing 0 is interpreted as a 1. by reading these 8 bits, the current value of the counter is read. 23 timer 1 enable post-scalar: set to enable timer1 post scalar. if enabled, an interrupts will be generated after t1con[31-24] periods as defined by t1ld. cleared to disable timer1 post scalar. 22-20 these bits are reserved and should be written as 0 by user code 19 post-scalar compare flag (read only). set if the number of timer1 overflows is equal to the number written to the post-scalar 18 timer 1 interrupt source set to select interrupt generation from post-scalar counter cleared to select interrupt generation direct from timer1 17 event select bit: set by user to enable time capture of an event cleared by user to disable time capture of an event 16-12 event select range, 0 to 31. the events are as described in table 46. timer event capture clock select: 000 core clock ( default ) 001 low power 32.768khz oscillator 010 gpio_8 11-9 011 gpio_5 8 count up: set by user for timer 1 to count up cleared by user for timer 1 to count down (default) 7 timer1 enable bit: set by user to enable timer 1 cleared by user to di sable timer 1 (default) 6 timer 1 mode: set by user to operate in periodic mode. cleared by user to operate in free-running mode (default) format: 00 binary (default) 01 reserved 10 hr:min:sec:hundredths C 23 hours to 0 hour 5-4 11 hr:min:sec:hundredths C 255 hours to 0 hour pre-scalar: 0000 source clock / 1 (default) 0100 source clock / 16 1000 source clock / 256 3-0 1111 source clock / 32768
preliminary technical data aduc7030/aduc7033 rev. pre | page 88 of 150 timer2 - wake-up timer timer2 is a 32-bit wake-up timer, count-down or count-up, with a programmable prescalar. the pre-scalar is clocked directly from 1 of 4 clock sources, namely, the core clock (default selection), the low power 32.768khz oscillator, external 32.768khz watch crystal, or the precision 32.768khz oscillator. the selected clock source can be scaled by a factor of 1, 16, 256 or 32768. the wake-up timer will continue to run when the core clock is disabled. this gives a minimum resolution of 48.83ns when operating at cd zero, the core is operating at 20.48mhz, and with a prescalar of 1. the counter can be formatted as plain 32-bit value or as hours:minutes:seconds:hundreths. timer2 reloads the value from t2ld either when timer2 overflows, or immediately when t2clri is written. timer2 interface consists of four mmrs: - t2ld and t2val are 32-bit registers and hold 32-bit unsigned integers. t2val is read-only. - t2clri is an 8-bit register. writing any value to this register will clear the timer2 interrupt. - t2con is the configuration mmr described in table 36 below. timer2 load registers: name: t2ld address: 0xffff0340 default va lu e: 0x00000000 access: read/write function: t2ld is a 32-bit register, which holds the 32 bit value that is loaded into the counter. timer2 clear register: name: t2clri address: 0xffff034c access: wr ite only function: this 32-bit, write-only mmr is written (with any value) by user code to refresh (reload) timer2. timer2 value register: name: t2val address: 0xffff0344 default va lu e: 0xffffffff access: read only function: t2val is a 32-bit register which holds the current value of timer2. 0 5994-032 prescaler 1, 16, 256, or 32768 timer2 irq 32-bit up/down counter precision 32.768khz oscillator low power 32.768khz oscillator core clock external 32.768khz watch crystal 32-bit load timer2 value figure 32. timer 2 block diagram
preliminary technical data aduc7030/aduc7033 rev. pre | page 89 of 150 timer2 control register: name: t2con address: 0xffff0348 default value: 0x0000 access: read/write function: this 16-bit mmr configures the mode of operation of timer2 table 49. t2con mmr bit descriptions bit description 15-11 reserved clock source select: 00 core clock ( default ) 01 low power 32.768khz oscillator 10 external 32.768khz watch crystal 10-9 11 precision 32.768khz oscillator 8 count up: set by user for timer 2 to count up cleared by user for timer 2 to count down (default) 7 timer2 enable bit: set by user to enable timer 2 cleared by user to di sable timer 2 (default) 6 timer 2 mode: set by user to operate in periodic mode cleared by user to operate in free-running mode (default) format: 00 binary ( default ) 01 reserved 10 hr:min:sec:hundredths C 23 hours to 0 hour (only valid with a 32khz clock) 5-4 11 hr:min:sec:hundredths C 255 hours to 0 hour (only valid with a 32khz clock) prescalar: 0000 source clock / 1 (default) 0100 source clock / 16 1000 source clock / 256 ( this setting should be us ed in conjunction timer2 formats 1,0 and 1,1 ) 3-0 1111 source clock / 32768
aduc7030/aduc7033 preliminary technical data rev. pre | page 90 of 150 timer3 - watchdog timer timer3 has two modes of operation, normal mode and watchdog mode. the watchdog timer is used to recover from an illegal software state. once enabled it requires periodic servicing to prevent it from forcing a reset of the processor. timer3 reloads the value from t3ld either when timer3 overflows, or immediately when t3clri is written. normal mode: the timer3 in normal mode is identical to timer0, in 16-bit mode of operation, except for the clock source. the clock source is the low power 32.768khz oscillator and can be scaled by a factor of 1, 16, or 256. watch d o g mo d e: watchdog mode is entered by setting t3con[5]. timer3 decrements from the timeout value present in t3ld register until zero. the maximum timeout is 512 seconds, using the maximum pre-scalar /256 and full-scale in t3ld. user software should only configure a minimum timeout period of 30msecs. this is to avoid any conflict with flash/ee memory page erase cycles, which require 20ms to complete a single page erase cycle, and kernel execution. if t3val reaches 0, a reset or an interrupt occurs, depending on t3con[1]. to avoid a reset or an interrupt event, any value must be written to t3clri before t3val reaches zero. this reloads the counter with t3ld and begins a new timeout period. once watchdog mode is entered, t3ld and t3con are write- protected. these two registers can not be modified until a power on reset event, resets the watchdog timer, after any other reset event, the watchdog timer continues to count. the watchdog timer should be configured in the initial lines of user code to avoid an infinite loop of watchdog resets. user software should only configure a minimum timeout period of 30msecs. timer3 is automatically halted during jtag debug access and will only recommence counting once jtag has relinquished control of the arm7 core. by default, timer3 continues to count during power-down. this may be disabled by setting bit zero in t3con. it is recommended that the default value is used, i.e. that the watchdog timer continues to count during power-down. 05994-033 prescaler 1, 16, 256 timer3 irq watchdog reset 16-bit up/down counter low power 32.768khz 16-bit load timer3 value figure 33. timer3 block diagram timer3 interface: timer3 interface consists of four mmrs: - t3con is the configuration mmr described in table 37 - t3ld and t3val are 16-bit registers (bit 0 to 15) and hold 16-bit unsigned integers. t3val is read-only. - t3clri is an 8-bit register. writing any value to this register will clear the timer3 interrupt in normal mode or will reset a new timeout period in watchdog mode timer3 load register: name: t3ld address: 0xffff0360 default va lu e: 0x0040 access: read/write function: this 16-bit mmr holds the timer3 reload value
preliminary technical data aduc7030/aduc7033 rev. pre | page 91 of 150 timer3 value register: name: t3val address: 0xffff0364 default va lu e: 0x0040 access: read only function: this 16-bit, read-only mmr holds the currenttimer3 count value. timer3 clear register: name: t3clri address: 0xffff036c access: wr ite only function: this 16-bit, write-only mmr is written (with any value) by user code to refresh(reload) timer3 in watchdog mode to prevent a watchdog timer reset event. timer3 control register: name: t3con address: 0xffff0368 default value: 0x0000 access: read/write function: the 16-bit mmr configures the mode of operation of timer3 as is described in detail in table 50. table 50. t3con mmr bit definition bit description 15-9 these bits are reserved and should be written as 0 by user code 8 count up/down enable set by user code to configure timer3 to count up cleared by user code to configure timer3 to count down 7 timer3 enable set by user code to enable timer 3 cleared by user code to disable timer 3 6 timer3 operating mode set by user code to configure time r3 to operate in periodic mode cleared by user to configure timer3 to operate in free-running mode 5 watchdog timer mode enable set by user code to enable watchdog mode cleared by user code to disable watchdog mode 4 reserved this bit is reserved and should be written as 0 by user code 3-2 timer3 clock(32.768khz) pre-scalar 00 source clock / 1 ( default ) 01 source clock / 16 10 source clock / 256 11 reserved 1 watchdog timer irq enable set by user code to produce an irq instea d of a reset when the watchdog reaches 0 cleared by user code to disable the irq option 0 pd_off set by the user code to stop timer3 when the periph erals are powered down via bit 4 in the powcon mmr. cleared by the user code to enable timer3 when the pe ripherals are powered down via bit 4 in the powcon mmr.
aduc7030/aduc7033 preliminary technical data rev. pre | page 92 of 150 timer4 - sti timer timer4 is a general purpose 16-bit count-up/down timer with a programmable prescalar. timer4 may be clocked from the core clock, or the low power 32.768khz oscillator, with a prescalar of 1, 16, 256 or 32,768. timer4 has a capture register (t4cap), which can be triggered by a selected irqs source initial assertion. once triggered, the current timer value is copied to t4cap, and the timer keeps running. this feature can be used to determine the assertion of an event with increased accuracy. timer4 may also be used to drive the sti (serial test interface) peripheral. timer4 interface consists of five mmrs: - t4ld, t4val and t4cap are 16-bit registers and hold 16-bit unsigned integers. t4val and t4cap are read-only. - t4clri is an 8-bit register. writing any value to this register will clear the interrupt - t4con is the configuration mmr described in table 35 05994-034 prescaler 1, 16, 256, or 32768 sti timer4 irq 16-bit up/down counter low power 32.768khz oscillator core clock frequency 16-bit load timer4 value capture irq[31:0] figure 34.. timer 4 block diagram timer4 load registers: name: t4ld address: 0xffff0380 default va lu e: 0x00000 access: read/write function: t4ld is a 16-bit register, which holds the 16-bit value that is loaded into the counter. timer4 clear register: name: t4clri address: 0xffff038c access: wr ite only function: this 8-bit, write-only mmr is written (with any value) by user code to refresh(reload) timer4. timer4 value register: name: t4val address: 0xffff0384 default va lu e: 0xffff access: read only function: t4val is a 16-bit register which holds the current value of timer4. timer4 capture register: name: t4cap address: 0xffff0390 default va lu e: 0x0000 access: read only function: this is a 16-bit register, which holds the 32-bit value captured by an enabled irq event.
preliminary technical data aduc7030/aduc7033 rev. pre | page 93 of 150 timer4 control register: name: t4con address: 0xffff0388 default value: 0x00000000 access: read/write function: this 32-bit mmr configures the mode of operation of timer4. table 51. t4con mmr bit description bit description 31-18 reserved 17 event select bit: set by user to enable time capture of an event cleared by user to disable time capture of an event 16-12 event select range, 0 to 31 the events are as described in table 46. timer event capture 11-10 reserved clock select 0 core clock (default) 9 1 low power 32.768khz oscillator 8 count up: set by user for timer 4 to count up cleared by user for timer 4 to count down (default) 7 timer4 enable bit: set by user to enable timer 0 cleared by user to disable timer 0 (default) 6 timer 4 mode: set by user to operate in periodic mode cleared by user to operate in free-running mode. default mode 5-4 reserved prescalar: 0000 source clock / 1 (default) 0100 source clock / 16 1000 source clock / 256 3-0 1111 source clock / 32768
aduc7030/aduc7033 preliminary technical data rev. pre | page 94 of 150 general purpose i/o the aduc7030/aduc7033 features 9 general purpose bi- directional i/o pins (gpio). in general, many of the gpio pins have multiple functions which can be configured by user code. by default, the gpio pins are configured in gpio mode. all gpio pins have an internal pull up resistor and their sink capability is 0.8ma and they can source 0.1ma. the 9 gpio are grouped into three ports, port0, port1 and port2. port0 is 5 bits wide. port1 and port2 are both 2 bits wide. the gpio assignment within each port is detailed in table 52. a typical gpio structure is shown figure 35. external interrupts are present on gp0, gp5, gp7 and gp8. this interrupts are level triggered and are active high. these interrupts are not latched, therefore the interrupts source must be present until either irqsta or fiqsta are interrogated. the interrupt source must be active for at least 1 cd divided core clock to guarantee recognition. all port pins are configured and controlled by 4 sets (1 set for each port) of four port specific mmrs: - gpxcon: port x control register - gpxdat: port x configuration and data register - gpxset: data set port x - gpxclr: data clear port x where x corresponds to the port number 0,1 or 2 during normal operation, user code can control the function and state of the external gpio pins via these general purpose registers. all gpio pins will retain their external (high or low) during power-down (powcon) mode. 05994-035 1 only available on gp0, gp5, gp7, and gp8. gpio reg_dvdd output drive enable gpxdat[31:24] output data gpxdat[23:16] input data gpxdat[7:0] gpio irq 1 figure 35. aduc7030/aduc7033 gpio
preliminary technical data aduc7030/aduc7033 rev. pre | page 95 of 150 table 52. external gpio pin to in ternal port signal assignments gpio pin port signal functionality ( defined by gpxcon ) general purpose i/o gpio_0 p0.0 irq0 ss , slave select i/o for spi general purpose i/o gpio_1 p0.1 sclk, serial clock i/o for spi general purpose i/o gpio_2 p0.2 miso, master input, slave output for spi general purpose i/o gpio_3 p0.3 mosi, master output, slave input for spi general purpose i/o gpio_4 p0.4 eclk , a 2.56mhz clock output p0.5 1 high voltage serial interface port 0 p0.6 1 high voltage serial interface general purpose i/o gpio_5 p1.0 irq1 rxd pin for uart general purpose i/o port 1 gpio_6 p1.1 txd pin for uart general purpose i/o gpio_7 p2.0 irq4 lin/bsd output pin. used to read directly from lin pin for conformance testing. general purpose i/o gpio_8 p2.1 irq5 lin/bsd hv input pin. used to directly drive lin pin for conformance testing. general purpose i/o gpio_11 2 p2.4 2 lin/bsd input pin general purpose i/o gpio_12 2 p2.5 2 lin/bsd output pin general purpose i/o port 2 gpio_13 1 p2.6 1 sti data output 1 these signals are internal signals only and do not appear on an external pin. these pins are used along with hvcon as the 2-wi re interface to the high voltage interface circuits. 2 these pins/signals are internal signals only and do not appear on an external pin. both signls are used to provide external pi n diagnostic write (gpio_12) and read- back (gpio_11) capability.
aduc7030/aduc7033 preliminary technical data rev. pre | page 96 of 150 gpio port0 control register: name: gp0con address: 0xffff0d00 default value: 0x11100000 access: read/write function: the 32-bit mmr selects the pin function for each port0 pin. table 53. gp0con mmr bit designations bit description 31-29 reserved these bits are reserved and should be written as 0 by user code 28 reserved this bit is reserved and should be written as 1 by user code 27-25 reserved these bits are reserved and should be written as 0 by user code 24 internal p0.6 enable bit this bit must be set to 1 by user software to enable the hi gh voltage serial interface before using the hvcon and hvdat registered high voltage interface 23-21 reserved these bits are reserved and should be written as 0 by user code 20 internal p0.5 enable bit this bit must be set to 1 by user software to enable the hi gh voltage serial interface before using the hvcon and hvdat registered high voltage interface 19-17 reserved these bits are reserved and should be written as 0 by user code 16 gpio_4 function select bit this bit is cleared by user code to 0 to configure the gpio_4 pin as a general purpose i/o (gpio) pin this bit is set to 1 by user code to configure the gpio_4 pin as eclk enab ling a 2.56mhz clock output on this pin 15-13 reserved these bits are reserved and should be written as 0 by user code 12 gpio_3 function select bit this bit is cleared by user code to 0 to configure the gpio_3 pin as a general purpose i/o (gpio) pin this bit is set to 1 by user code to co nfigure the gpio_3 pin as mosi, master o utput, slave input data for the spi port 11-9 reserved these bits are reserved and should be written as 0 by user code 8 gpio_2 function select bit this bit is cleared to 0 by user co de to configure the gpio_2 pin as a general purpose i/o (gpio) pin this bit is set to 1 by user code to configure the gpio_2 pin as miso, master input, slave output da ta for the spi port 7-5 reserved these bits are reserved and should be written as 0 by user code 4 gpio_1 function select bit this bit is cleared to 0 by user co de to configure the gpio_1 pin as a general purpose i/o (gpio) pin this bit is set to 1 by user code to configure the gpio_1 pin as sclk, serial clock i/o for the spi port 3-1 reserved these bits are reserved and should be written as 0 by user code 0 gpio_0 function select bit this bit is cleared to 0 by user co de to configure the gpio_0 pin as a general purpose i/o (gpio) pin this bit is set to 1 by user code to configure the gpio_0 pin as ss , serial clock i/o for the spi port
preliminary technical data aduc7030/aduc7033 rev. pre | page 97 of 150 gpio port1 control register: name: gp1con address: 0xffff0d04 default value: 0x10000000 access: read/write function: the 32-bit mmr selects the pin function for each port1 pin. table 54. gp1con mmr bit designations bit description 31-5 reserved these bits are reserved and should be written as 0 by user code 4 gpio_6 function select bit this bit is cleared by user code to 0 to configure the gpio_6 pin as a general purpose i/o (gpio) pin this bit is set to 1 by user code to configure the gpio_6 pin as txd, transmit data for uart serial port 3-1 reserved these bits are reserved and should be written as 0 by user code 0 gpio_5 function select bit this bit is cleared by user code to 0 to configure the gpio_5 pin as a general purpose i/o (gpio) pin this bit is set by user code to 1 to configure the gpio_5 rxd. re ceive data for uart serial port
aduc7030/aduc7033 preliminary technical data rev. pre | page 98 of 150 gpio port2 control register: name: gp2con address: 0xffff0d08 default value: 0x01000000 access: read/write function: the 32-bit mmr selects the pin function for each port2 pin. table 55. gp2con mmr bit designations bit description 31- 25 reserved these bits are reserved and should be written as 0 by user code 24 gpio_13 function select bit this bit is set to 1 by user co de to route the sti data output to the sti pin. if this bit is clear to 0 by user code, then the sti data will not be routed to the external sti pin even if the sti interface itself is enabled correctly. 23- 21 reserved these bits are reserved and should be written as 0 by user code 20 gpio_12 function select bit this bit is cleared to 0 by user code to route the lin/bsd trans mit data to an internal genera l purpose i/o (gpio_12) pad which can then be written via the gp2dat mmr. this co nfiguration is used in bsd mode to allo w user code write output data to the bsd interface and can also be used to support diagnostic writ e capability to the high-voltage i/o pins(see hvcfg1[2:0]). this bit is set to 1 by user co de to route the uart txd (transmit data) to the lin/bsd data pin. this configuration is used in lin mode. 19- 17 reserved these bits are reserved and should be written as 0 by user code 16 gpio_11 function select bit this bit is cleared to 0 by user code to internally disable the lin/bsd input data path. in this configuration gpio_11 is used to support diagnostic read-back on all external high-voltage i/o pins (see hvcfg1[2:0]) this bit is set to 1 by user code to ro ute input data from the lin/bsd interface to both the lin/bsd hardware timing/synchroniz ation logic and to the uart rxd (receive data). this mode must be configured by us er code when using lin or bsd modes. 15- 5 reserved these bits are reserved and should be written as 0 by user code 4 gpio_8 function select bit this bit is cleared by user code to 0 to configure the gpio_8 pin as a general purpose i/o (gpio) pin this bit is set by user code to 1 to rout e the lin/bsd input data to the gpio_8 pin. this mode can be used to drive the lin tra nsceiver interface as a standalone component without any interaction from mcu or uart. 3-1 reserved these bits are reserved and should be written as 0 by user code 0 gpio_7 function select bit this bit is cleared by user code to 0 to configure the gpio_7 pin as a general purpose i/o (gpio) pin this bit is set by user code to 1 to rout e data driven into the gpio_7 pin through the on-chip lin transceiver to be output at the lin/bsd pin. this mode can be used to drive the lin transceive r interface as a standalone comp onent without any interaction fro m mcu or uart.
preliminary technical data aduc7030/aduc7033 rev. pre | page 99 of 150 gpio port0 data register: name: gp0dat address: 0xffff0d20 default value: 0x000000xx access: read/write function: this 32-bit mmr configures the direction of the gpio pins assigned to port0 (see table 52). this register also sets the output value for gpio pins configured as outputs and reads the status of gpio pins configured as inputs. table 56. gp0dat mmr bit descriptions bit description 31-29 reserved these bits are reserved and should be written as 0 by user code 28 port 0.4 direction select bit this bit is cleared to 0 by user code to configure the gpio pin a ssigned to p0.4 as an input. this bit is set to 1 by user co de to configure the gpio pin a ssigned to p0.4 as an output. 27 port 0.3 direction select bit this bit is cleared to 0 by user code to configure the gpio pin a ssigned to p0.3 as an input. this bit is set to 1 by user co de to configure the gpio pin a ssigned to p0.3 as an output. 26 port 0.2 direction select bit this bit is cleared to 0 by user code to configure the gpio pin a ssigned to p0.2 as an input. this bit is set to 1 by user co de to configure the gpio pin a ssigned to p0.2 as an output. 25 port 0.1 direction select bit this bit is cleared to 0 by user code to configure the gpio pin a ssigned to p0.1 as an input. this bit is set to 1 by user co de to configure the gpio pin a ssigned to p0.1 as an output. 24 port 0.0 direction select bit this bit is cleared to 0 by user code to configure the gpio pin a ssigned to p0.0 as an input. this bit is set to 1 by user co de to configure the gpio pin a ssigned to p0.0 as an output. 23-21 reserved these bits are reserved and should be written as 0 by user code 20 port 0.4 data output the value written to this bit appears dire ctly on the gpio pin assigned to p0.4. 19 port 0.3 data output the value written to this bit appears dire ctly on the gpio pin assigned to p0.3. 18 port 0.2 data output the value written to this bit appears dire ctly on the gpio pin assigned to p0.2. 17 port 0.1 data output the value written to this bit appears dire ctly on the gpio pin assigned to p0.1. 16 port 0.0 data output the value written to this bit appears dire ctly on the gpio pin assigned to p0.0. 15-5 reserved these bits are reserved and should be written as 0 by user code 4 port 0.4 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p0.4. user code should write 0 to this bit. 3 port 0.3 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p0.3. user code should write 0 to this bit. 2 port 0.2 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p0.2. user code should write 0 to this bit. 1 port 0.1 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p0.1. user code should write 0 to this bit. 0 port 0.0 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p0.0. user code should write 0 to this bit.
aduc7030/aduc7033 preliminary technical data rev. pre | page 100 of 150 gpio port1 data register: name: gp1dat address: 0xffff0d30 default value: 0x000000xx access: read/write function: this 32-bit mmr configures the direction of the gpio pins assigned to port1 (see table 52). this register also sets the output value for gpio pins configured as outputs and reads the status of gpio pins configured as inputs. table 57. gp1dat mmr bit descriptions bit description 31-26 reserved these bits are reserved and should be written as 0 by user code 25 port 1.1 direction select bit this bit is cleared to 0 by user code to configure the gpio pin a ssigned to p1.1 as an input. this bit is set to 1 by user co de to configure the gpio pin a ssigned to p1.1 as an output. 24 port 1.0 direction select bit this bit is cleared to 0 by user code to configure the gpio pin a ssigned to p1.0 as an input. this bit is set to 1 by user co de to configure the gpio pin a ssigned to p1.0 as an output. 23-18 reserved these bits are reserved and should be written as 0 by user code 17 port 1.1 data output the value written to this bit appears dire ctly on the gpio pin assigned to p1.1. 16 port 1.0 data output the value written to this bit appears dire ctly on the gpio pin assigned to p1.0. 15-2 reserved these bits are reserved and should be written as 0 by user code 1 port 1.1 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p1.1. user code should write 0 to this bit. 0 port 1.0 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p1.0. user code should write 0 to this bit.
preliminary technical data aduc7030/aduc7033 rev. pre | page 101 of 150 gpio port2 data register: name: gp2dat address: 0xffff0d40 default value: 0x000000xx access: read/write function: this 32-bit mmr configures the direction of the gpio pins assigned to port2 (see table 52). this register also sets the output value for gpio pins configured as outputs and reads the status of gpio pins configured as inputs. table 58 :gp2dat mmr bit descriptions bit description 31 reserved, this bit is reserved and should be written as 0 by user code 30 port 2.6 direction select bit this bit is cleared to 0 by user code to configure the gpio pin assi gned to p2.6 as an input. this bit is set to 1 by user code to configur e the gpio pin assigned to p2.6 as an output. 29 port 2.5 direction select bit this bit is cleared to 0 by user code to configure the gpio pin a ssigned to p2.5 as an input. this bit is set to 1 by user code to conf igure the gpio pin assigned to p2.5 as an output. this configuration is used to suppor t diagnostic write capability to the high-voltage i/o pins. 28 port 2.4 direction select bit this bit is cleared to 0 by user code to configure the gpio pin assigned to p2.4 as an input. this config uration is used to sup port diagnostic read-back capability from the hi gh-voltage i/o pins(see hvcfg1[2:0]). this bit is set to 1 by user code to configure the gpio pin assigned to p2.4 as an output. 27- 26 reserved these bits are reserved and should be written as 0 by user code 25 port 2.1 direction select bit this bit is cleared to 0 by user code to configure the gpio pin a ssigned to p2.1 as an input. this bit is set to 1 by user co de to configure the gpio pin a ssigned to p2.1 as an output. 24 port 2.0 direction select bit this bit is cleared to 0 by user code to configure the gpio pin a ssigned to p2.0 as an input. this bit is set to 1 by user co de to configure the gpio pin a ssigned to p2.0 as an output. 23 reserved, this bit is reserved and should be written as 0 by user code 22 port 2.6 data output the value written to this bit appears dire ctly on the gpio pin assigned to p2.6 21 port 2.5 data output the value written to this bit appears dire ctly on the gpio pin assigned to p2.5. 20- 18 reserved these bits are reserved and should be written as 0 by user code 17 port 2.1 data output the value written to this bit appears dire ctly on the gpio pin assigned to p2.1. 16 port 2.0 data output the value written to this bit appears dire ctly on the gpio pin assigned to p2.0. 15-7 reserved, these bits are reserved and should be written as 0 by user code 6 port 2.6 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p2.6. user code should write 0 to this bit. 5 port 2.5 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p2.5. user code should write 0 to this bit. 4 port 2.4 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p2.4. user code should write 0 to this bit. 3-2 reserved, these bits are reserved and should be written as 0 by user code 1 port 2.1 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p2.1. user code should write 0 to this bit. 0 port 2.0 data input this bit is a read-only bit that reflects the current status of the gpio pin assigned to p2.0. user code should write 0 to this bit.
aduc7030/aduc7033 preliminary technical data rev. pre | page 102 of 150 gpio port0 set register: name: gp0set address: 0xffff0d24 access: wr ite only function: this 32-bit mmr allow user code to individually bit address external gpio pins to set them high only. user code can do this via the gp0set mmr without having to modify or maintain the status of any other gpio pins as user code would need to do when using gp0dat. table 59. gp0set mmr bit descriptions bit description 31-21 reserved these bits are reserved and should be written as 0 by user code 20 port 0.4 set bit this bit is set to 1 by user code to set the external gpio_4 pin high. if user software clears this bi t to 0, this will have no effect on the external gpio_4 pin. 19 port 0.3 set bit this bit is set to 1 by user code to set the external gpio_3 pin high. if user software clears this bi t to 0, this will have no effect on the external gpio_3 pin. 18 port 0.2 set bit this bit is set to 1 by user code to set the external gpio_2 pin high. if user software clears this bi t to 0, this will have no effect on the external gpio_2 pin. 17 port 0.1 set bit this bit is set to 1 by user code to set the external gpio_1 pin high. if user software clears this bi t to 0, this will have no effect on the external gpio_1 pin. 16 port 0.0 set bit this bit is set to 1 by user code to set the external gpio_0 pin high if user software clears this bi t to 0, this will have no effect on the external gpio_0 pin. 15-0 reserved these bits are reserved and should be written as 0 by user code
preliminary technical data aduc7030/aduc7033 rev. pre | page 103 of 150 gpio port1 set register: name: gp1set address: 0xffff0d34 access: wr ite only function: this 32-bit mmr allow user code to individually bit address external gpio pins to set them high only. user code can do this via the gp1set mmr without having to modify or maintain the status of any other gpio pins as user code would need to do when using gp1dat. table 60. gp1set mmr bit descriptions bit description 31-18 reserved these bits are reserved and should be written as 0 by user code 17 port 1.1 set bit this bit is set to 1 by user code to set the external gpio_6 pin high. if user software clears this bi t to 0, this will have no effect on the external gpio_6 pin. 16 port 1.0 set bit this bit is set to 1 by user code to set the external gpio_5 pin high if user software clears this bi t to 0, this will have no effect on the external gpio_5 pin. 15-0 reserved these bits are reserved and should be written as 0 by user code
aduc7030/aduc7033 preliminary technical data rev. pre | page 104 of 150 gpio port2 set register: name: gp2set address: 0xffff0d44 access: wr ite only function: this 32-bit mmr allow user code to individually bit address external gpio pins to set them high only. user code can do this via the gp2set mmr without having to modify or maintain the status of any other gpio pins as user code would need to do when using gp2dat. table 61. gp2set mmr bit descriptions bit description 31-23 reserved these bits are reserved and should be written as 0 by user code 22 port 2.6 set bit this bit is set to 1 by user code to set the external gpio_13 pin high. if user software clears this bi t to 0, this will have no effect on the external gpio_13 pin. 21 port 2.5 set bit this bit is set to 1 by user code to set the external gpio_12 pin high if user software clears this bi t to 0, this will have no effect on the external gpio_12 pin. 20-18 reserved these bits are reserved and should be written as 0 by user code 17 port 2.1 set bit this bit is set to 1 by user code to set the external gpio_8 pin high. if user software clears this bi t to 0, this will have no effect on the external gpio_8 pin. 16 port 2.0 set bit this bit is set to 1 by user code to set the external gpio_7 pin high if user software clears this bi t to 0, this will have no effect on the external gpio_7 pin. 15-0 reserved these bits are reserved and should be written as 0 by user code
preliminary technical data aduc7030/aduc7033 rev. pre | page 105 of 150 gpio port0 clear register: name: gp0clr address: 0xffff0d28 access: wr ite only function: this 32-bit mmr allows user code to individually bit address external gpio pins to clear them low only. user code can do this via the gp0clr mmr without having to modify or maintain the status of any other gpio pins as user code would need to do when using gp0dat table 62. gp0clr mmr bit descriptions bit description 31-21 reserved these bits are reserved and should be written as 0 by user code 20 port 0.4 clear bit this bit is set to 1 by user code to clear the external gpio_4 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_4 pin. 19 port 0.3 clear bit this bit is set to 1 by user code to clear the external gpio_3 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_3 pin. 18 port 0.2 clear bit this bit is set to 1 by user code to clear the external gpio_2 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_2 pin. 17 port 0.1 clear bit this bit is set to 1 by user code to clear the external gpio_1 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_1 pin. 16 port 0.0 clear bit this bit is set to 1 by user code to clear the external gpio_0 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_0 pin. 15-0 reserved these bits are reserved and should be written as 0 by user code
aduc7030/aduc7033 preliminary technical data rev. pre | page 106 of 150 gpio port1 clear register: name: gp1clr address: 0xffff0d38 access: wr ite only function: this 32-bit mmr allows user code to individually bit address external gpio pins to clear them low only. user code can do this via the gp1clr mmr without having to modify or maintain the status of any other gpio pins as user code would need to do when using gp1dat. table 63. gp1clr mmr bit descriptions bit description 31-18 reserved these bits are reserved and should be written as 0 by user code 17 port 1.1 clear bit this bit is set to 1 by user code to clear the external gpio_6 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_6 pin. 16 port 1.0 clear bit this bit is set to 1 by user code to clear the external gpio_5 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_5 pin. 15-0 reserved these bits are reserved and should be written as 0 by user code
preliminary technical data aduc7030/aduc7033 rev. pre | page 107 of 150 gpio port2 clear register: name: gp2clr address: 0xffff0d48 access: wr ite only function: this 32-bit mmr allows user code to individually bit address external gpio pins to clear them low only. user code can do this via the gp2clr mmr without having to modify or maintain the status of any other gpio pins as user code would need to do when using gp2dat. table 64. gp2clr mmr bit descriptions bit description 31-23 reserved these bits are reserved and should be written as 0 by user code 22 port 2.6 clear bit this bit is set to 1 by user code to clear the external gpio_13 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_8 pin. 21 port 2.5 clear bit this bit is set to 1 by user code to clear the external gpio_12 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_7 pin. 20-18 reserved these bits are reserved and should be written as 0 by user code 17 port 2.1 clear bit this bit is set to 1 by user code to clear the external gpio_8 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_8 pin. 16 port 2.0 clear bit this bit is set to 1 by user code to clear the external gpio_7 pin low. if user software clears this bi t to 0, this will have no effect on the external gpio_7 pin. 15-0 reserved these bits are reserved and should be written as 0 by user code
preliminary technical data aduc7030/aduc7033 rev. pre | page 108 of 150 high voltage peripheral control interface the aduc7030/aduc7033 integrates a number of high voltage circuit functions, which are controlled and monitored via a registered interface consisting of 2 mmrs, namely, hvcon and hvdat. the hvcon register acts as a command byte interpreter allowing the microcontroller to indirectly read or write 8-bit data (the value in hvdat) from/to one of 4 high voltage status/configuration registers. it should be noted that these high voltage registers are not mmrs but are so called indirect registers that can only be accessed (as the name suggests) indirectly via the hvcon and hvdat mmrs. the physical interface between the hvcon register and the indirect high voltage registers is a 2-wire (data and clock) serial interface based on a 2.56mhz serial clock. therefore, there is a finite, 10secs (maximum) latency between the mcu core writing a command into hvcon and that command or data reaching the indirect high voltage registers. there is also a finite 10secs latency between the mcu core writing a command into hvcon and indirect register data being read back into the hvdat register. a busy bit (bit0 of the hvcon when read by mcu) can be polled by the mcu to confirm when a read/write command has completed. the following high voltage circuit functions are controlled and monitored via this interface and figure 36 below describes the top-level architecture of the high voltage interface and related circuits. precision oscillator wa k e - up pi n f u nc t i on a l it y power supply monitor low voltage flag lin operating modes sti diagnostics high voltage diagnostics high voltage attenuator/buffer circuit high voltage temperature monitor 05994-036 arm7 mcu and peripherals high-voltage interface mmrs hvcon hvdat precision oscillator hvcfg0[6] lvf hvcfg0[2] lin modes psm hvcfg0[3] attenuator and buffer hvcfg1[5] hvcfg1[7] hv temp monitor hvcfg1[6] hvcfg1[3] hvcfg0 (indirect) high-voltage registers hvcfg1 hvsta hvmon serial interface controller serial data serial clock high voltage interrupt controller psm?hvsta[5] wu?hvsta[4] over temp?hvsta[3] lin s-sct?hvsta[2] sti s-sct?hvsta[1] wu s-sct?hvsta[0] irq3 (irqen[16]) high voltage diagnostic controller wu diagnostic i/p hvcfg0[4] sti diagnostic i/p p2.6 lin diagnostic i/p p2.5 wu diagnostic o/p hvmon[7] sti diagnostic o/p hvmon[5] lin diagnostic o/p p2.4 hvcfg0[5] hvcfg0[1:0] wu i/o control hvcfg0[4] hvcfg1[4] hvcfg1[4] sti i/o control hvcfg1[3] figure 36. high voltage interface, top level block diagram
preliminary technical data aduc7030/aduc7033 rev. pre | page 109 of 150 high voltage interface control register: name: hvcon address: 0xffff0804 default value: updated by kernel access: read/write function: this 8-bit register acts as a command byte interpreter for the high voltage control interface. bytes written to this register are interpreted as read or write commands to a set of 4 indirect registers related to the high voltage circuits. the hvdat register is used to store data to be written to or read back from the indirect registers table 65. hvcon mmr write bit designations bit description 7-0 command byte interpreted as 0x00 read back high voltage register hvcfg0 into hvdat 0x01 read back high voltage register hvcfg1 into hvdat 0x02 read back high voltage sta tus register hvsta into hvdat 0x03 read back high voltage sta tus register hvmon into hvdat 0x08 write the value in hvdat to the high voltage register hvcfg0 0x09 write the value in hvdat to the high voltage register hvcfg1 table 66. hvcon mmr read bit designations bit description 7-3 reserved 2 transmit command to high voltage die status: 1 command completed successfully 0 command failed 1 read command from high voltage die status: 1 command completed successfully 0 command failed 0 bit 0 (read only) busy bit when user code reads this register, bit0 should be interpreted as the busy signal for the high-voltage interface. this bit can be used to determine if a read request has completed. high vo ltage (read/write) commands as described above should not be written to hvcon unless busy=0. busy = 1, high voltage interface is busy and has not comple ted the previous command written to hvcon. bit 1 and bit 2 are not valid. busy = 0, high voltage interface is not busy and has comple ted the command written to hvcon. bit 1 and bit 2 are valid.
aduc7030/aduc7033 preliminary technical data rev. pre | page 110 of 150 high voltage data register: name: hvdat address: 0xffff080c default value: updated by kernel access: read/write function: hvdat is a 12-bit register that is used to hold data to be written indirectly to and read indirectly from the following high voltage interface registers. table 67. hvdat mmr bit designations bit description 11-8 command to which high voltage data, hvdat[7-0], is associated with. these bits are read only and should be written as zeros. 0x00 read back high voltage register hvcfg0 into hvdat 0x01 read back high voltage register hvcfg1 into hvdat 0x02 read back high voltage sta tus register hvsta into hvdat 0x03 read back high voltage sta tus register hvmon into hvdat 0x08 write the value in hvdat to the high voltage register hvcfg0 0x09 write the value in hvdat to the high voltage register hvcfg1 7-0 high voltage data to read/write
preliminary technical data aduc7030/aduc7033 rev. pre | page 111 of 150 high voltage configuration0 register: name: hvcfg0 address: indirectly addressed via the hvcon high voltage interface default value: 0x00 access: read/write function: this 8-bit register controls the function of high voltage circuits on the aduc7030/aduc7033. this register is not an mmr and does not appear in the mmr memory map. it is accessed via the hvcon registered interface. data to be written to this register is loaded via the hvdat mmr and data is read back from this register via the hvdat mmr. table 68. hvcfg0 bit designations bit description 7 wake/sti thermal shutdown disable: this bit is set to 1 to disable the automatic shutdown of the wake/sti driver when a thermal event occurs. this bit is cleared to 0 to enable the automatic shutdo wn of the wake/sti driver when a thermal event occurs. 6 precision oscillator enable bit this bit is set to 1 to enable the precis ion, 131khz oscillator. the oscillator start- up time is typically 70secs (including h v interface latency of 10secs) this bit is cleared to 0 to power do wn the precision, 131khz oscillator 5 bsd mode enable bit this bit is cleared to 0 to enable an intern al (lin) pull-up resistor on the lin/bsd pin this bit is set to 1 to disable the internal (lin) pull-up and configure the lin/bsd pin for bsd operation 4 wu assert bit this bit is set to 1 to assert the external wu pin high. this bit is cleared to 0 to pull the external wu pin low via an internal 10k ? pull-down resistor. 3 psm enable bit this bit is cleared to 0 to disable the po wer supply (voltage at the vdd pin) monitor this bit is set to 1 to enable the power supply (voltage at the vdd pin) monitor. if irq3 (irqen[16] is enabled the psm will generate an interrupt if the voltage at the vdd pin drops below 6.0v. 2 low voltage flag enable bit this bit is cleared to 0 to disable the low voltage flag function this bit is set to 1 to enable the low voltage flag function. th e low voltage flag can be interrogated via hvmon[3] after power up to determine if the reg_dvdd vo ltage previously dropped below 2.1v 1-0 lin operating mode these bits enable/disable the lin driver. 0 0 lin disabled 0 1 reserved C (not lin v2.0 compliant) 1 0 lin enabled 1 1 lin enabled, fast mo de (>20kbd) - not lin compliant
aduc7030/aduc7033 preliminary technical data rev. pre | page 112 of 150 high voltage configuration1 register: name: hvcfg1 address: indirectly addressed via the hvcon high voltage interface default value: 0x00 access: read/write function: this 8-bit register controls the function of high voltage circuits on the aduc7030/aduc7033. this register is not an mmr and does not appear in the mmr memory map. it is accessed via the hvcon registered interface, data to be written to this register is loaded via hvdat and data is read back from this register via hvdat. table 69. hvcfg1 bit designations bit description 7 attenuator enable bit this bit is cleared to 0 to disable the internal voltage attenuator and attenuator buffer. this bit is set to 1 to enable the internal voltage attenuator and attenuator buffer. 6 high voltage temperature monitor the high voltage temperature monitor is an un-calibrated te mperature monitor located on-chip close to the high voltage circuits. this monitor is completely separate to the on-chip, precision temperature sensor (controlled via adc1con[7,6]) and allows user code to monitor die temperature change clos e the hottest part of the ad uc7030/aduc7033 die. the monitor generates a typical output voltage of 600mv at 25 c and has a negative temperature co efficient of typically -2.1mv/ c this bit is set to 1 to enable the on-chip, high voltage temper ature monitor. once enabled this voltage out temperature monitor is routed directly to the voltage channel adc. this bit is cleared to 0 to disable the on-chip, high voltage temperature monitor. 5 voltage channel short enable bit this bit is set to 1 to enable an intern al short (at the attenuator, before adc inp ut buffer) on the voltage channel adc and al low noise be measured as a self-diagnostic test. this bit is cleared to 0 to disable an internal short on the voltage channel. 4 wu and sti read back enable bit this bit is cleared to 0 to disable input capability on the external wu/sti pin this bit is set to 1 to enable input capability on the external wu/sti pin. in this mode, a rising or falling edge transition o n the wu/sti pin will generate a high voltage interrupt. once this bi t is set, the state of the wu/sti pin can be monitored via the hvmon register (hvmon[7] and hvmon[5]). 3 hv-io driver enable bit this bit is set to 1 to re-enable any high voltage-io pins (lin/bsd/sti/wu) that have been disabled as a result of an short cir cuit current event(event must last lo nger than 20secs for lin/bsd/sti pins and 400usecs for wu pin). this bit must also be set to 1 to re-enable the wu/sti pins if disabled by a thermal event. it should be noted that this bit must be set to clear any pend ing interrupt generated by the short circuit event (even if the e vent has passed) as well as re-enabl ing the high-voltage io pins. this bit is cleared to 0 automatically. 2 enable/disable short circuit protection (lin/bsd & sti) this bit is set to 1 to enable passive short circuit protection on lin pin. in this mode, a short circuit event on the lin/bsd pin will generate a hv interrupt (irq3-irqen[16]), assert the approp riate status bit in hvsta but will not disable the short circui ting pin. this bit is cleared to 0 to enable active short circuit protection on lin/bsd pin. in this mode, a short circuit event the lin/bsd pin will generate a hv interrupt (irq3-irqen[16]), assert the ap propriate status bit in hvsta an d automatically disable the sho rt circuiting pin. once disabled, the i/o pin can only be re-enabled by writing to hvcfg1[3]. 1 wu pin time-out ( monoflop ) counter enable/disable this bit is set to disable the wu i/o time-out counter. this bit is cleared to enable a time-out counter which automati cally de-asserts the wu pin 1.3 seconds after user code has asserted the wu pin via hvcfg0[4]. 0 wu o/c diagnostic enable this bit is set to enable an internal wu i/o diagnostic pull-up resistor to the vdd pi n thus allowing detection of an o/c condi tion on the wu pin. this bit is cleared to disable an intern al wu i/o diagnostic pull-up resistor
preliminary technical data aduc7030/aduc7033 rev. pre | page 113 of 150 high voltage monitor register: name: hvmon address: indirectly addressed via the hvcon high voltage interface default value: 0x00 access: read only function: this 8-bit read only register reflects the current status of enabled high voltage related circuits and functions on the aduc7030/33. this register is not an mmr and does not appear in the mmr memory map. it is accessed via the hvcon registered interface, and data is read back from this register via hvdat. table 70. hvmon bit designations bit description 7 wu pin diagnostic read-back once enabled via hvcfg1[4], this read only bit will reflect the state of the external wu pin. 6 over temperature this bit will be 0 if a thermal shutdown event has not occurred. this bit will be 1 if a thermal shutdown event has occurred. 5 sti pin diagnostic read-back once enabled via hvcfg1[4], this read only bit will reflect the state of the external sti pin. 4 buffer enabled this bit will be 0 if the voltage channel adc input buffer is disabled this bit will be 1 if the voltage channel adc input buffer is enabled 3 low voltage flag status bit (only valid if enabled via hvcfg0[2]) this bit will be 0 on power-on if reg_dvdd had dropped below 2. 1v. in this state, ram contents can be deemed corrupt. this bit will be 1 on power-on if reg_dvdd had not dropped below 2. 1v. in this state, ram contents can be deemed valid. it will only be cleared by re-enabling the low voltage flag in hvcfg0[2] 2 lin/bsd short circuit status flag: this bit will be 0 if the lin/bsd driver is operating normally. this bit will be 1 if the lin/bsd driver has experienced a short circuit condition and will be cleared automatically by writing to hvcfg1[3]. 1 sti short circuit status flag: this bit will be 0 if the sti driver is operating normally. this bit will be 1 if the sti driver has experienced a short circ uit condition and is cleared automatically by writing to hvcfg 1[3]. 0 wake short circuit status flag: this bit will be 0 if the wake driver is operating normally. this bit will be 1 if the wake driver has experienced a short circuit condition.
aduc7030/aduc7033 preliminary technical data rev. pre | page 114 of 150 high voltage status register: name: hvsta address: indirectly addressed via the hvcon high voltage interface default value: 0x00 access: read only. this register should only be read on a high voltage interrupt. function: this 8-bit read only register reflects a change of state of all the corresponding bit in the hvmon register. this register is not an mmr and does not appear in the mmr memory map. it is accessed via the hvcon registered interface, and data is read back from this register via hvdat. it should be noted that in response to a high voltage interrupt event, the high voltage interrupt controller simultaneously and automatically loads the current value of the high voltage status register (hvsta) into the hvdat register. table 71. hvsta bit designations bit description 7-6 reserved these bits should not be used and are reserved for future use. 5 psm status bit (only valid if enabled via hvcfg0[3]) this bit is 0 if the voltage at the vdd pin stays above 6.0v this bit will be 1 if the voltage at the vdd pin drops below 6.0v. please note that this bit is not latched an d the irq needs to be enabled to detect it. 4 wu request status bit (only valid if enabled via hvcfg1[4]) once enabled via hvcfg1[4], this bit will be set to 1 to indicate that a rising or falling edge transition on the wu pin genera ted a high voltage interrupt. 3 over temperature (always enabled) this bit will be 0 if a thermal shutdown event has not occurred. this bit will be 1 if a thermal shutdown event has occurred. all high voltage (lin/bsd, wu & sti) pin drivers will be automatic ally disabled once a thermal shutdown has occurred. 2 lin/bsd short circuit status flag this bit will be 0 during normal lin/bsd operation and is cleared automatically by reading the hvsta register. this bit will be 1 if a lin/bsd short circuit is detected. in th is condition, the lin driver will be automatically disabled. 1 sti short circuit status flag: this bit will be 0 if the sti driver is operating normally and is cleared automatically by reading the hvsta register. this bit will be 1 if the sti driver has experienced a short circuit condition. 0 wake short circuit status flag this bit will be 0 during normal wake operation this bit will be 1 if a wake short circuit is detected.
preliminary technical data aduc7030/aduc7033 rev. pre | page 115 of 150 wake-up (wu) the wu pin is a high voltage gpio controlled via hvcon and hvdat. wake-up (wu) pin circuit description the wu pin is configured by default as an output with an internal 10k ? pull-down resistor and high side fet driver. the wu pin in its default mode of operation is specified to generate an active high system wake-up request by forcing the external system wu bus high. user code can assert the wu output by writing directly to hvcfg0[4]. it should be noted the output will only respond after the 10secs latency through the (serial communication based) high voltage interface. the internal fet is capable of sourcing significant current and therefore a substantial on-chip self-heating can occur if this driver is asserted for a long time period. for this reason a monoflop, a 1.3-second timeout timer, has been included. by default the monoflop is enabled and will disable the wake driver after 1.3 seconds. it is possible to disable the monoflop via hvcfg1[1]. if the wake monoflop is disabled, then the wake driver should be disabled after 1.3s. the wu pin also features a short circuit detection feature. when the wake pin sources mo re than 100ma typically for 400s a high voltage interrupt will be generated with hvmon[0] set. a thermal shutdown event disables the wu driver. the wu driver must be re-enabled manually after a thermal event via hvcfg1[3]. the wu pin can be configured in i/o mode by writing a 1 to hvcfg1[4]. in this mode, a rising or falling edge will immediately generate a high voltage interrupt. hvmon[7] directly reflects the state of the external wu pin. this comparator has a trip level of 3v typ . 05994-037 v dd internal sense resistor short circuit trip reference short circuit protection output control hvmon[0] normal hvcfg0[4] normal hvmon[7] 400s glitch immunity 3v enable read-back hvcfg1[4] internal 10k ? resistor r1 6.6k ? r2 3.3k ? io_vss 6k ? o/c diagnostic resistor external wu pin external wake bus c load 91nf r load 1k ? external current-limit resistor 39 ? hvcfg1[0] figure 37. wu circuit, block diagram
aduc7030/aduc7033 preliminary technical data rev. pre | page 116 of 150 handling interrupts from the high voltage peripheral control interface an interrupt controller is also integrated with the high voltage circuits. if enabled via irqen[16], one of 6 high voltage sources can assert the high voltage interrupt (irq3) signal and interrupt the mcu core. while the mcu response to this interrupt event is, as normal, to vector to the irq or fiq interrupt vector address. the high voltage interrupt controller simultaneously and automatically loads the current value of the high voltage status register (hvsta) into the hvdat register. during this time the busy bit in hvcon[0] is set to indicate the transfer is in progress and will be cleared after 10secs to indicate the hvsta contents are now available in hvdat. the interrupt handler can therefore poll the busy bit in hvcon until it de-asserts. once the busy bit is cleared, hvcon[1] must be checked to ensure the data was read correctly. then the hvdat register can be read. at this time hvdat will then hold the value of the hvsta register. the status flags can then be interrogated to determine the exact source of the high voltage interrupt and the appropriate action taken. low voltage flag (lvf) the aduc7030 features a low voltage flag (lvf), which when enabled allows the user to monitor reg_dvdd. when enabled via hvcfg0[2], the low voltage flag may be monitored via hvmon[3]. if reg_dvdd drops below 2.1v, then hvmon[3] is cleared. if reg_dvdd drops below 2.1v the ram contents are corrupted. once the low voltage flag is enabled, it is only reset by reg_dvdd dropping below 2.1v or the disabling of the lvf functionality via hvcfg0[2]. high voltage diagnostics it is possible to diagnosis fault conditions on the wake, lin and sti bus as follows. table 72. high voltage diagnostics high voltage pin fault condition method result short between lin/sti and vbat drive lin low lin/sti short circuit interrupt will be generated after 20s if more than 100ma is drawn continuously. lin/sti short between lin/sti and gnd drive lin high lin/sti read back reads back low. short between wake and vbat drive wake low read back high in hvmon[7] short between wake and gnd drive wake high wake short circuit interrupt will be generated after 400us if more than 100ma typically is sourced wake open circuit enable oc diagnostic resistor with wake disabled. hvmon[7] will be cleared if load is connected and set if wake is open circuited
preliminary technical data aduc7030/aduc7033 rev. pre | page 117 of 150 uart serial interface the aduc7030/aduc7033 features a 16450 compatible uart. the uart is a full-duplex universal asynchronous receiver/transmitter. a uart performs serial-to-parallel conversion on data characters received from a peripheral device, and parallel-to-serial conversion on data characters received from the arm7tdmi. the uart features a fractional divider, which facilitates high accuracy baud rate generation, and a network addressable mode. the uart functionality is made available on gpio_5, rxd, and gpio_6, txd, of the aduc7030/aduc7033. the serial communication adopts a asynchronous protocol that supports various word length, stop bits and parity generation options selectable in the configuration register. baud rate generation the aduc7030/aduc7033 features two methods of generating the uart baud rate: 1. normal 450 uart baud rate generation. 2. aduc7030/aduc7033 fractional divider these two methods are explained in detail below. normal 450 uart baud rate generation the baud rate is a divided version of the core clock using the value in comdiv0 and comdiv1 mmrs (16-bit value, dl). the standard baud rate generator formula is dl mhz baudrate cd = (1) table 73 gives some common baud rate values: table 73. baud rate using the standard baud rate generator baud rate cd dl actual baud rate % error 9600 0 0x43 9552 0.50% 19200 0 0x21 19394 1.01% 115200 0 0x6 106667 7.41% 9600 3 0x8 10000 4.17% 19200 3 0x4 20000 4.17% 115200 3 0x1 80000 30.56% aduc7030/aduc7033 fractional divider: the fractional divider combined with the normal baud-rate generator allows the generation of accurate, high speed, baud- rates. 05994-038 /2 /(m+n/2048) /16dl uart core clock fben figure 38. fractional divider baud rate generation calculation of the baud rate using fractional divider is as follows: ) 2048 ( 2 16 2 48 . 20 n m dl mhz baudrate cd + = 2 16 2 48 . 20 2048 = + dl b audrate mhz n m cd table 74 gives some common baud rate values. table 74. baud rate using the fractional baud rate generator baud rate cd dl m n actual baud rate % error 9600 0 42h 1 21 9598.55 0.015% 19200 0 21h 1 21 19197.09 0.015% 115200 0 5h 1 228 115177.51 0.0195%
aduc7030/aduc7033 preliminary technical data rev. pre | page 118 of 150 uart register definition the uart interface consists of 9 registers namely: - comtx: 8-bit transmit register - comrx: 8-bit receive register - comdiv0: divisor latch (low byte) comtx, comrx and comdiv0 share the same address location. comtx and comtx can be accessed when bit 7 in comcon0 register is cleared. comdiv0 can be accessed when bit 7 of comcon0 is set. - comdiv1: divisor latch (high byte) - comcon0: line control register - comsta0: line status register - comien0: interrupt enable register - comiid0: interrupt identification register - comdiv2: 16-bit fractional baud divide register uart tx register: name: comtx address: 0xffff0700 access: wr ite only function: this 8-bit register is written to, to transmit data via the uart. uart rx register: name: comrx address: 0xffff0700 default va lu e: 0x00 access: read only function: this 8-bit register is read from to receive data transmitted via the uart. uart divisor latch register 0: name: comdiv0 address: 0xffff0700 default va lu e: 0x00 access: read/write function: this 8-bit register contains the least significant byte of the divisor latch witch controls the baud rate at which the uart operates. uart divisor latch register 1: name: comdiv1 address: 0xffff0704 default va lu e: 0x00 access: read/write function: this 8-bit register contains the most significant byte of the divisor latch witch controls the baud rate at which the uart operates.
preliminary technical data aduc7030/aduc7033 rev. pre | page 119 of 150 uart control register 0: name: comcon0 address: 0xffff070c default value: 0x00 access: read/write function: this 8-bit register controls the operation of the uart in conjunction with comcon1. table 75. comcon0 mmr bit descriptions bit name description 7 dlab divisor latch access set by user to enable access to comdiv0 and comdiv1 registers cleared by user to disable acce ss to comdiv0 and comdiv1 and en able access to comrx, comtx and comien0 6 brk set break. set by user to force txd to 0 cleared to operate in normal mode 5 sp stick parity set by user to force pa rity to defined values: 1 if eps = 1 and pen = 1 0 if eps = 0 and pen = 1 4 eps even parity select bit set for even parity cleared for odd parity 3 pen parity enable bit: set by user to transmit and check the parity bit cleared by user for no parity transmission or checking 2 stop stop bit set by user to transmit 1.5 stop bit if the word length is 5 bits or 2 stop bits if the word length is 6, 7 or 8 bits. the receiver checks the first stop bit only, regardless of the number of stop bits selected cleared by user to generate 1 stop bit in the transmitted data 1-0 wls word length select: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits
aduc7030/aduc7033 preliminary technical data rev. pre | page 120 of 150 uart control register 1: name: comcon1 address: 0xffff0710 default value: 0x00 access: read/write function: this 8-bit register controls the operation of the uart in conjunction with comcon0. table 76. comcon1 mmr bit descriptions bit name description uart input mux 00 rxd driven by lin input required for lin communications via lin pin 01 reserved 10 rxd driven by gp5 required for serial communications via gp5 pin ( rxd ) 7-6 11 reserved 5 reserved C not used 4 loopback loop back set by user to enable loop back mode. in loop-back mode, the txd is forced high. 3-0 reserved C not used
preliminary technical data aduc7030/aduc7033 rev. pr e | page 121 of 150 uart status register 0: name: comsta0 address: 0xffff0714 default value: 0x60 access: read only function: this 8-bit read only register reflects the current status on the uart. table 77. comsta0 mmr bit descriptions bit name description 7 reserved 6 temt comtx and shift register empty status bit set automatically if comtx and the sh ift register are empty. this bit indicates that the data has been transmitted, i.e. is no more present in the shift register. cleared automatically wh en writing to comtx 5 thre comtx empty status bit. set automatically if comtx is empty. comtx can be written is soon as this bit gets set, the previous data might not have been transmitted yet and st ill be present in the shift register. cleared automatically wh en writing to comtx 4 bi break indicator set when sin is held low for more than the maximum word length cleared automatically 3 fe framing error set when invalid stop bit cleared automatically 2 pe parity error set when a parity error occurs cleared automatically 1 oe overrun error set automatically if data are overwrite before been read cleared automatically 0 dr data ready set automatically when comrx is full cleared by reading comrx
aduc7030/aduc7033 preliminary technical data rev. pre | page 122 of 150 uart interrupt enable register 0: name: comien0 address: 0xffff0704 default value: 0x00 access: read/write function: the 8-bit register enables/disables the individual uart interrupt sources table 78. comien0 mmr bit descriptions bit name description 7-4 reserved C not used 3 edssi reserved C should be written as 0 2 elsi rx status interrupt enable bit set by user to enable generation of an interrupt if any of comsta0[3:0] are set cleared by user 1 etbei enable transmit buffer empty interrupt set by user to enable interrupt wh en buffer is empty during a transmi ssion i.e. when comsta[5] is set cleared by user 0 erbfi enable receive buffer full interrupt set by user to enable interrupt wh en buffer is full during a reception cleared by user uart interrupt identifi cation register 0: name: comiid0 address: 0xffff0708 default value: 0x01 access: read only function: this 8-bit register reflects the source of the uart interrupt table 79. comiid0 mmr bit descriptions bit 2-1 status bits bit 0 nint priority definition clearing operation 00 1 no interrupt 11 0 1 receive line status interrupt read comsta0 10 0 2 receive buffer full interrupt read comrx 01 0 3 transmit buffer empty interrupt wr ite data to comtx or read comiid0 00 0 4 modem status interrupt read comsta1 register
preliminary technical data aduc7030/aduc7033 rev. pre | page 123 of 150 uart fractional divider register: name: comdiv2 address: 0xffff072c default value: 0x0000 access: read/write function: this 16-bit register controls the operation of the aduc7030/aduc7033s fractional divider table 80. comdiv2 mmr bit descriptions bit name description 15 fben fractional baud rate generator enable bit set by user to enable the fr actional baudrate generator cleared by user to generate baudrate usin g the standard 450 uart baudrate generator 14-13 reserved 12-11 fbm[1-0] m. if fbm = 0, m = 4 10-0 fbn[10-0] n
aduc7030/aduc7033 preliminary technical data rev. pre | page 124 of 150 serial peripheral interface the aduc7030 features a complete hardware serial peripheral interface (spi) on-chip. spi is an industry standard synchronous serial interface, which allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. the spi interface is only operational with core clock divider bits (powcon[2:0]= 0 or 1). the spi port can be configured for master or slave operation and consists of four pins, which are multiplexed with four gpio. the four spi pins are miso, mosi, sclk and ss . the pins to which this signals are connected are shown in table 81. table 81. spi output pins pin signal description gp0 ( gpio mode 1 ) ss chip select gp1 ( gpio mode 1 ) sclk serial clock gp2 ( gpio mode 1 ) miso master out, slave in gp3 ( gpio mode 1 ) mosi master in, slave out miso (master in, slave out data i/o pin) the miso (master in slave out) pin is configured as an input line in master mode and an output line in slave mode. the miso line on the master (data in) should be connected to the miso line in the slave device (data out). the data is transferred as byte wide (8-bit) serial data, msb first. mosi (master out, slave in pin) the mosi (master out slave in) pin is configured as an output line in master mode and an input line in slave mode. the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in). the data is transferred as byte wide (8-bit) serial data, msb first. sclk (serial clock i/o pin) the master serial clock (sclk) is used to synchronize the data being transmitted and received through the mosi sclk period. therefore, a byte is transmitted/received after eight sclk periods. the sclk pin is configured as an output in master mode and as an input in slave mode. in master mode polarity and phase of the clock are controlled by the spicon register, and the bit-rate is defined in the spidiv register as follow: ) 1 ( 2 48 . 20 spidiv mhz f k serialcloc + = equation 1. spi baud rate calculation the maximum speed of the spi clock is dependant on the clock divider bits and is summarized in table 82. table 82. spi speed vs. clock di vider bits in master mode cd bits 0 1 spidiv 0x05 0x0b max sclk (mhz) 1.667 0.833 in slave mode, the spicon register must be configured with the phase and polarity of the expected input clock. the slave accepts data from an external master up to 5.12 mb at cd = 0. the formula to determine the maximum speed is as follow: 4 hclk k serialcloc f f = in both master and slave modes, data is transmitted on one edge of the scl signal and sampled on the other. therefore, it is important that the polarity and phase are configured the same for the master and slave devices. chip select ( ss ) input pin in spi slave mode, a transfer is initiated by the assertion of ss which is an active low input signal. the spi port will then transmit and receive 8-bit data until the transfer is concluded by de-assertion of ss . in slave mode ss is always an input. spi registers definition the following mmr registers are used to control the spi interface: - spicon: 16-bit control register - spista: 8-bit read only status register - spidiv: 8-bit serial clock divider register - spitx: 8-bit write only transmit register - spirx: 8-bit read only receive register
preliminary technical data aduc7030/aduc7033 rev. pre | page 125 of 150 spi control register: name: spicon address: 0xffff0a10 default value: 0x0000 access: read/write function: the 16-bit mmr configures the serial peripheral interface. table 83. spicon mmr bit descriptions bit description 15-13 reserved 12 continuous transfer enable set by user to enable continuous transfer. in master mode, the transfer will continue until no valid data is available in the tx register. ss will be asserted and remain asserted for the duration of each 8-bi t serial transfer until tx is empty cleared by user to disable continuous transfer. ea ch transfer consists of a single 8-bit seri al transfer. if valid data exists in the spitx register then a new transfer is initiated after a stall period 11 loop back enable set by user to connect miso to mosi and test software cleared by user to be in normal mode 10 slave output enable set by user to enable the slave output cleared by user to disable slave output 9 slave select input enable set by user in master mode to enable the output 8 spirx overflow overwrite enable set by user, the valid data in the rx register is overwritten by the new serial byte received cleared by user, the new serial byte received is discarded 7 spitx underflow mode set by user to transmit the previous data cleared by user to transmit 0 6 transfer and interrupt mode (master mode) set by user to initiate transfer with a write to the spitx register. interrupt will occur when tx is empty cleared by user to initiate transfer with a read of the spirx register. interrupt wi ll occur when rx is full 5 lsb first transfer enable bit set by user the lsb is transmitted first cleared by user the msb is transmitted first 4 reserved 3 serial clock polarity mode bit set by user, the serial clock idles high cleared by user the serial clock idles low 2 serial clock phase mode bit set by user, the serial clock pulses at the beginning of each serial bit transfer cleared by user, the serial clock pulses eat end of each serial bit transfer 1 master mode enable bit set by user to enable master mode cleared by user to enable slave mode 0 spi enable bit set by user to enable the spi cleared to disable the spi
aduc7030/aduc7033 preliminary technical data rev. pre | page 126 of 150 spi status register: name: spista address: 0xffff0a00 default value: 0x00 access: read only function: the 8-bit mmr represents the current status of the serial peripheral interface. table 84. spista mmr bit descriptions bit description 7-6 reserved 5 spirx data register overflow status bit set if spirx is overflowing cleared by reading spisrx register 4 spirx data register irq set automatically if bit 3 or 5 are set cleared by reading spirx register 3 spirx data register full status bit set automatically if a valid data is present in the spirx register cleared by reading spirx register 2 spitx data register underflow status bit set automatically if sp itx is under flowing cleared by writing in the spitx register 1 spitx data register irq set automatically if bit 0 is clear or bit 2 is set cleared by writing in the spitx register or if finished transmission disabling the spi 0 spitx data register empty status bit set by writing to spitx to send data. this bit is set during transmission of data cleared when spitx is empty spi receive register: name: spirx address: 0xffff0a04 default value: 0x00 access: read only function: this 8-bit mmr contains the data received via the serial peripheral interface. spi transmit register: name: spitx address: 0xffff0a08 access: wr ite only function: this 8-bit mmr is written to, to transmit data via the serial peripheral interface.
preliminary technical data aduc7030/aduc7033 rev. pre | page 127 of 150 spi divider register: name: spidiv address: 0xffff0a0c default value: 0x1b access: read/write function: the 8-bit mmr represents the frequency of the serial peripheral interface is operating at. for more information on the calculation of the baud rate, please refer to equation 1.
aduc7030/aduc7033 preliminary technical data rev. pre | page 128 of 150 serial test interface the aduc7030/aduc7033 incorporate a single pin, serial test interface (sti) port that can be used for end-customer evaluation or diagnostics on finished production units. the sti port transmits from 1 to 6 bytes of data in 12-bit packets. as shown in figure 39 below, each transmission packet includes a start bit, the transmitted byte (8 bits), an even parity bit and two stop bits. the sti data is transmitted on the sti pin and the baud rate is determined by the overflow rate of timer4. the sti port is configured and controlled via six mmrs, namely: - stikey0: serial test interface key 0. - stikey1: serial test interface key 1. - stidat0: data (16-bit) 0 C holds 2 bytes - stidat1: data (16-bit) 1 - holds 2 bytes - stidat2: data (16-bit) 2 - holds 2 bytes - sticon: controls the serial test interface sti key0 register: name: stikey0 address: 0xffff0880 access: wr ite only function: the stikey0 mmr is used in conjunction with the stikey1 mmr to protect the sticon mmr. stikey0 must be written with 0x0007 immediately before any attempt is made to write to sticon. stikey1 must be written with 0x00b9 immediately after sticon is written to ensure the sticon write sequence is completed successfully. if stikey0 is not written, is written out of sequence or is written incorrectly, any subsequent write to the sticon mmr will be ignored. sti key1 register: name: stikey1 address: 0xffff0888 access: wr ite only function: the stikey01 mmr is used in conjunction with the stikey0 mmr to protect the sticon mmr. stikey1 must be written with 0x00b9 immediately after any attempt is made to write to sticon. stikey0 must be written with 0x0007 immediately before sticon is written to ensure the sticon write sequence is completed successfully. if stikey1 is not written, is written out of sequence or is written incorrectly, any previous write to the sticon mmr will be ignored. sti data0 register: name: stidat0 address: 0xffff088c default va lu e: 0x0000 access: read/write function: the stidat0 mmr is a 16-bit register which is used to hold the first and second data bytes that will be transmitted on the sti pin once the sti port is enabled. the first byte to be transmitted will occupy bits0-7 and the second byte will occupy bits 8-15. 05994-039 parity bit start bit sti byte0 sti byte1 sti byte2 pairty bit with 2 stop bits figure 39. serial adc test interface example- 3 byte transmission
preliminary technical data aduc7030/aduc7033 rev. pre | page 129 of 150 sti data1 register: name: stidat1 address: 0xffff0890 default va lu e: 0x0000 access: read/write function: the stidat1 mmr is a 16-bit register which is used to hold the third and fourth data bytes that will be transmitted on the sti pin once the sti port is enabled. the third byte to be transmitted will occupy bits0-7 and the fourth byte will occupy bits8-15. sti data2 register: name: stidat1 address: 0xffff0894 default va lu e: 0x0000 access: read/write function: the stidat2 mmr is a 16-bit register which is used to hold the fifth and sixth data bytes that will be transmitted on the sti pin once the sti port is enabled. the fifth byte to be transmitted will occupy bits0-7 and the sixth byte will occupy bits8-15. sti control register: name: sticon address: 0xffff0884 default value: 0x0000 access: read/write access, write protected by 2 key registers (stikey0 and stikey1). a write access to sticon is only completed correctly if the following triple write sequence is followed 1. stikey0 mmr is written with 0x7 2. sticon is written 3. the sequence is completed by writing 0xb9 to stikey1 function: the sti control mmr is an 16-bit register that configures the mode of operation of the serial test interface. note: gpio_13 must be configured for sti operation in gp2con for sti communications. table 85. sticon mmr bit descriptions bit description 16- 9 reserved these bits are reserved for future use and should be written as 0 by user code 8-5 state bits, read only if the interface is in the middle of a transmission, these bits will not be 0 4-2 number of bytes to transmit these bits select the number of bytes that will be transmitted. user code must subsequently write the bytes to be transmitted i nto the stidat0,1 and 2 mmrs 0, 0, 0 1-byte transmission 0, 0, 1 2-byte transmission 0, 1, 0 3-byte transmission 0, 1, 1 4-byte transmission 1, 0, 0 5-byte transmission 1, 0, 1 6-byte transmission 1 reset serial test interface this bit is set to a 1 to reset the serial test interface, a subsequent read of sticon will return all 0s this bit is set to a 0 by user co de during normal serial test interface operation, by power-on default 0 serial test interface enable this bit is set to a 1 by user code to enable the serial test interface this bit is set to 0 by user code to disable the serial test interface
aduc7030/aduc7033 preliminary technical data rev. pre | page 130 of 150 serial test interface output structure the serial test interface is a high voltage output, which incorporates a low side driver, short circuit protection and diagnostic pin read-back capability. the output driver circuit configuration is shown in figure 40 below. 05994-040 pin read-back hvsta[7] sti transmit gp2con[24] ref1 short circuit protection control hvcfg1[2] sti figure 40. sti output structure using the serial test interface data will only begin transmission once configuration of the sti port has been completed in the following sequence: a. configure timer4 for baud rate generation b. correctly enable sticon using stikey0 and stikey1 for secure access c. required bytes to be tran smitted are written into stidat0, stidat1 and stidat2. timer 4 is configured with the correct load value to generate an overflow at the required baud rate. if the sti port is being used to transmit adc conversion results, then the baud rate must be sufficient to output each adc result (16-bits) prior to next adc conversion result being available. for example, if the adc is sampling at 1khz, then the baud rate has to be sufficient to output 36 bits, 3 x 8 bits (16-bit adc result and a checksum byte for example) + 3 x 1 start bits + 3 x 1 parity bits + 3 x 2stop bits = 36 bits. therefore, the serial test interface must transmit data at greater than 36kbps. the closest standard baud rate is 38.4kbps. therefore the reload value written to the timer4 load mmr (t4ld) is 0106h(267d). this value is calculated as shown below and is based on a pre-scalar of 1, using a core clock of 10.24mhz. drate desiredbau requency coreclockf ld t = = 10.24mhz/ 38.4kbps = 267 once the timer4 load value is written and the timer itself is configured and enabled using the t4con mmr, the sti port must be configured. the is done by writing to the sticon mmr in a specific sequence using the stikey0 and stikey1 mmrs as described earlier. finally, the sti port will not begin transmission until the required number of transmit bytes is written into the stidatx mmrs. as soon as sti starts transmitting, the value in the sticon mmr will change from the value initially written to this register. user code can ensure that all data is transmitted by continuously polling the sticon mmr until it reverts back to the value originally written to it. to disable the serial interface, user code must write a 0 to sticon[0].
preliminary technical data aduc7030/aduc7033 rev. pre | page 131 of 150 an example code segment configuring the sti port to transmit 5 bytes and then to transmit 2 bytes is shown below: t4ld = 267; // timer4 reload value t4con = 0xc0; // enable t4, selecting core clock in periodic mode stikey0 = 07; // sticon start write sequence sticon = 0x11; // enable and transmit 5 bytes stikey1 = 0xb9; // sticon complete write stidat0 = 0xaabb; // 5 bytes for stidat1 = 0xccdd; // transmission stidat2 = 0xff; while(sticon != 0x09) // wait for transmission to complete {} stikey0 = 07; // sticon start write sequence sticon = 0x05; // enable and transmit 2 bytes stikey1 = 0xb9; // sticon complete write stidat0 = 0xeeff; // 2 bytes for transmission while(sticon != 0x09) // wait for transmission to complete {}
aduc7030/aduc7033 preliminary technical data rev. pre | page 132 of 150 lin (local interconnect network) interface the aduc7030/aduc7033 features a high voltage physical interface between the arm7 mcu core and an external lin bus. the lin interface operates as a slave only interface operating from 1-20kbaud, and is compatible with the lin2.0 standard. the pull-up resistor required for a slave node is on- chip, reducing the need for external circuitry. the lin protocol is emulated using the on-chip uart, an irq, a dedicated lin timer and the high voltage transceiver which is also incorporated on-chip. this is shown in figure 41. the lin is clocked from the low power oscillator, for the break timer, and a 5mhz output from the pll which is used for the synch byte timing. lin mmr description the lin hardware synchronization (lhs) functionality is controlled via five mmrs. the function of each mmr is described below:. lhssta : lhs status register. this mmr contains information flags which describe the current status on the interface. lhscon0 : lhs control register 0. this mmr controls the configuration of the lhs timer. lhscon1 : lhs start and stop edge control register dictates which edge of the lin synchronization byte the lhs starts/stops counting. lhsval0 : lhs synchronization 16bit timer, which is controlled by lhscon0. lhsval1 : lhs break timer register 0 5994-041 gpio12 function select gp2con[20] gpio12 gp2dat[29] and gpsdat[21] aduc7030 uart lhs hardware aduc7030 rxd txd bpf internal short-circuit trip reference internal short-circuit sense resistor short-circuit control hvcfg1[2] output disable lin mode hvcfg0[1:0] input voltage threshold reference lin enable (internal pull-up) hvcfg0[5] four lin interrupt sources break lhssta[0] start lhssta[1] stop lhssta[2] break error lhssta[4] vdd rxd enable lhscon0[8] lhsval0 lhsval1 lhs interrupt irqen[7] 5mhz 131khz lhs interrupt logic vdd scr io_vss over voltage protection external lin pin master ecu protection diode master ecu pull-up c load figure 41. lin i/o, block diagram
preliminary technical data aduc7030/aduc7033 rev. pre | page 133 of 150 lin hardware synchronization status register: name: lhssta address: 0xffff0780 default value: 0x00000000 access: read only function: the lhs status register is a 32-bit register whose bits reflect the current operating status of the aduc7030/aduc7033 lin interface table 86. lhssta mmr bit descriptions bit description 31 - 7 reserved these read-only bits are reserved for future use 6 rising edge detected (bsd mode only) this bit is set to 1 by hardware to indicate a rising edge has been detected on the bsd bus. this bit is cleared to 0, after user code reads the lhssta mmr 5 lhs reset complete flag this bit is set to 1 by hardware to indicate a lhs reset command has completed successfully. this bit is cleared to 0, after user code reads the lhssta mmr 4 break field error this bit is set to 1 by hardware and generates an lhs interrup t (irqen[7]) when the 12-bit, break timer (lhsval1) register over flows to indicate the lin bus has stayed low too long thus indicating a possible lin bus error. this bit is cleared to 0, after user code reads the lhssta mmr 3 lhs compare interrupt this bit is set to 1 by hardware when the value in lhsval0 (l in synchronization bit timer) = the value in the lhscmp register. this bit is cleared to 0, after user code reads the lhssta mmr 2 stop condition interrupt this bit is set to 1 by hardware when a stop condition is detected. this bit is cleared to 0, after user code reads lhssta mmr 1 start condition interrupt this bit is set to 1 by hardware when a start condition is detected. this bit is cleared to 0, after user code reads lhssta mmr 0 break timer compare interrupt this bit is set to 1 by hardware when a valid lin break condit ion is detected. a lin break condition is generated when the lin break timer value reaches the break timer compare value (see lhsval1 description below). this bit is cleared to 0, after user code reads the lhssta mmr
aduc7030/aduc7033 preliminary technical data rev. pre | page 134 of 150 lin hardware synchronization control register 0: name: lhscon0 address: 0xffff0784 default value: 0x00000000 access: read/write function: the lhs control register is a 32-bit register that in conjunction with the lhscon1 register is used to configure the lin mode of operation table 87. lhscon0 mmr bit descriptions bit description 31-13 reserved these bits are reserved for future and shou ld be written as 0 by user software. 12 rising edge detected interrupt disable bsd mode: this bit is set to 1 to disable th e rising edge detected interrupt. this bit is cleared to 0 to enable the break rising edge detected interrupt lin mode: this bit is set to 1 to enable th e rising edge detected interrupt. this bit is cleared to 0 to disable the break rising edge detected interrupt 11 break timer compare interrupt disable: this bit is set to 1 to disable the break timer compare interrupt. this bit is cleared to 0 to enable the break timer compare interrupt 10 break timer error interrupt disable: this bit is set to 1 to disable the break timer error interrupt. this bit is cleared to 0 to enable the break timer error interrupt 9 lin transceiver, stand-alone test mode this bit is cleared to 0 by user code to operate the li n in normal mode, driven directly from the on-chip uart. this bit is set to 1 by user code to enab le external gpio_7 and gpio_8 pins to dr ive the lin transceiver txd and rxd respective ly, independent of the uart. the functions of gpio_7 and gpio_8 should first be configured by user code via gpio function select bits <0 and 4> in the gp2con register. 8 gate uart/bsd r/ w bit in lin mode (lhscon0[6] is cleared to 0): this bit is set to 1 by user code to disa ble the internal uart rxd (receive data) by gating it high until both the break field and subsequent lin sync byte have been detected. this ensures the uart will not receive any spurious serial data during break or sync field periods which will have to be flushed out of the uart before valid data fields can start to be received. this bit is set to 0 by user code to enab le the internal uart rxd (receive data) af ter the break field and subsequent lin sync byte have been detected so that the uart can receive the subsequent lin data fields. in bsd mode (lhscon0<6> is set to1): in bsd read-mode, this bit is set to 1 by user code to enable the generation of a break condition interrupt (lhssta[0]) on a rising edge of the bsd bus. in bsd read mode the break timer ( lhsval1) starts counting on the falling edge and stops counting on the rising edge. the generate of an inte rrupt on this rising edge allows user code determine if a 0, 1 or sync pulse width h as been received. it should also be noted that the break timer will also still generate an interrupt if the value in the lin break timer(lhsval1 read value) = the break t imer compare value (lhsval1 write value) and if the break timer overflows. this configuration can be used in bsd read mode detect fault conditions on the bsd bus. in bsd write mode, this bit is cleared to 0 by user code to disable the generation of break condition interrupts on a rising ed ge of the bsd bus (as is required in bsd read mode).in bsd wr ite mode, the lhs compare interrupt (lhssta[3]) is used to determine when the mcu should release the bsd bus when transmi tting data. if the break condition interrupt was still enabled it would generate an unwanted interrupt as soon as the bsd bus is de-asserted. as in bsd read mode, the break timer will stop counting on a rising edge so the break t imer can also be used in this mode to a llow user code confirm the pulse width in transmitted data bits. note: because of the finite propagation delay in the bsd transmit (from mcu to external pin) and receive (from external pin to mcu) paths, user code must not switch between bsd write and re ad modes until the mcu confirms the external bsd pin is de- asserted. failure to adhere to this recommendation may result in the generation of an inadvertent break condition interrupt
preliminary technical data aduc7030/aduc7033 rev. pre | page 135 of 150 bit description after user code switches from bsd write mode to bsd read mode. a stop condition interrupt could be used to ensure that this scenario is avoided. 7 sync timer stop edge type bit this bit is cleared to 0 by user code to stop the sync timer on the falling edge count configured via the lhscon1[7:4] register . this bit is set to 1 by user code to stop the sync timer on the rising edge count configured via the lhscon1[7:4] register. 6 mode of operation bit this bit is cleared to 0 by user code to select lin mode of operation this bit is set to 1 by user code to select bsd mode of operation 5 enable compare interrupt bit this bit is cleared to 0 by user code to disable compare interrupts this bit is set to 1 by user code to generate an lhs interr upt(irqen[7]) when the value in lhsval0 (lin synchronisation bit timer) = the value in the lhscmp register. the lhs compare inte rrupt bit lhssta[3] is set when this interrupt occurs. this configuration is used in bsd write mode to allow user code correctly time the output pulse widths of bsd bits to be transmitted . 4 enable stop interrupt this bit is cleared to 0 by user code to di sable interrupts when a stop condition occurs this bit is set to 1 by user code to genera te an interrupt when a stop condition occurs 3 enable start interrupt this bit is cleared to 0 by user code to disa ble interrupts when a start condition occurs this bit is set to 1 by user code to genera te an interrupt when a start condition occurs 2 lin sync enable bit this bit is cleared to 0 by user code to disable lhs functionality this bit is set to 1 by user code to enable lhs functionality 1 edge counter clear bit this bit is set to 1 by user co de to clear the internal edge counters in the lhs peripheral. this bit is cleared to 0 auto matically after a 15us delay. 0 lhs reset bit this bit is set to 1 by user code to reset all lhs logic to default conditions. this bit is cleared to 0 auto matically after a 15us delay.
aduc7030/aduc7033 preliminary technical data rev. pre | page 136 of 150 lin hardware synchronization control register 1: name: lhscon1 address: 0xffff078c default value: 0x00000032 access: read/write function: the lhs control register is a 32-bit register that in conjunction with the lhscon0 register is used to configure the lin mode of operation table 88. lhscon1 mmr bit descriptions bit description 31- 8 reserved these bits are reserved for future and shou ld be written as 0 by user software. 7-4 lin stop edge count these 4 bits are set by user code to the number of falling or rising edges on which to stop the internal lin synchronization co unter. the stop value of this counter can be read by user code via lhsv al0. the type of edge, either rising or falling, is configured by lhscon0[7]. the default value of these bits is 0x3 which configures the hardware to stop counting on the third falling edge. it should be noted that the first falling edge is taken as th e falling edge at the start of the lin break pulse. 3-0 lin start edge count these 4 bits are set by user code to the number of falling edges after which the internal lin synchronization timer will start counting. the stop value of this counter can be read by user code via lhs val0. the default value of these bits is 0x2 which configures th e hardware to start counting on the second falling edge. it should be noted that the first falling edge is taken as the falling e dge at the start of the lin break pulse. lin hardware synchronization timer0 register: name: lhsval0 address: 0xffff0788 default value: 0x0000 access: read only function: the 16-bit read only lhsval0 register holds the value of the internal lin synchronization timer. the lin synchronization timer is clocked from an internal 5mhz clock which is independent of core clock and baud-rate frequency. in lin mode, the value read by user code from the lhsval0 register can be used calculate the master lin baud-rate. this calculation can then be used to configure the internal uart baud-rate to ensure correct lin communication via the uart from the aduc 7030/aduc7033 slave to the lin master node
preliminary technical data aduc7030/aduc7033 rev. pre | page 137 of 150 lin hardware break timer1 register: name: lhsval1 address: 0xffff0790 default value: 0x000(read) or 0x047(write) access: read/write function: when user code reads this location, the 12-bit value returned is the value of the internal lin break timer, which is clocked directly from the on-chip low power (131khz) oscillator and times the lin break pulse. a negative edge on the lin bus or user code reading the lhsval1 will result in the timer and the register contents being reset to 0. when user code writes to this location, the 12-bit value is actually written not to the lin break timer but to a lin break compare register. in lin mode of operation the value in the compare register is continuously compared to the break timer value. a lin break interrupt (irqen[7] and lhssta[0]) is generated when the timer value reaches the compare value. after the break condition interrupt, the lin break timer continues to count until the rising edge of the break signal. if a rising edge is not detected and the 12-bit timer overflows (4096 x 1/131khz= 31msecs), a break field error interrupt (irqen[7] and lhssta[4]) will be generated. by default, the value in the compare register is 0x47, this corresponds to 11 x bit periods i.e. the minimum pulse width for a lin break pulse at 20kbps. for different baud rates, this value may be changed by writing to. it is also important to note that if a valid break interrupt is not received then subsequent sync pulse timing via lhsval0 register will not occur. lin hardware interface lin frame protocol the lin frame protocol is broken into 4 main categories: ? break symbol ? sync byte ? protected identifier ? data bytes the format of the frame header, break, synchronization byte and protected identifier are shown in figure 42. essentially, the embedded uart, lin hardware synchronization logic and the high voltage transceiver interface all combine on-chip to support and manage lin based transmissions and receptions. lin frame break symbol as shown in figure 43, the lin break symbol is used to signal the start of a new frame. it lasts at least 13-bit periods and a slave must be able to detect a break symbol, even if it expects data or is in the process of receiving data. the aduc7030/aduc7033 accomplishes this by using the lhsval1 break condition and break error detect functionality as described earlie r. the break period does not have to be accurately measured, but if a bus fault condition (bus held low) occurs, it must be flagged. lin frame synchronization byte the baud rate of the communication via lin is calculated from the sync byte. this can be se en in figure 44. the time between the first falling edge of the sync field and the fifth falling edge of the sync field is measured. this is then divided by eight to give the baud rate of the data that will be transmitted. the aduc7030/aduc7033 implements the timing of this sync byte in ha rdware. for more information on this feature, please refer to lin hardware synchronization. lin frame protected identifier after receiving the lin synch fiel d, the required baud rate for the uart is calculated. the uart is then configured, which allows the aduc7030/aduc7033 to receive the protected identifier, as shown in figure 45. the protected identifier consists of two sub-fields, the identifier and the identifier parity. the six-bit identifier contai ns the identifier of the target for the frame. the identifier sign ifies the number of data bytes to be either received or transmitted. the number of bytes is user configurable at system level design. the parity is calculated on the identifier, and is dependent on the revision of lin the system is designed for. lin frame data byte the data byte frame carries between one and eight bytes of data. the number of bytes contained in the frame will be dependent on the lin master. the data byte frame is split into data bytes as shown in figure 46.
aduc7030/aduc7033 preliminary technical data rev. pre | page 138 of 150 lin frame data transmission and reception once the break symbol and synchronization byte have being correctly received, data is transmitted and received via the comtx and comrx mmrs, after configuration of the uart to the required baud rate. to configure the uart for use with lin requires the use of the following uart mmrs: - comdiv0: divisor latch (low byte) - comdiv1: divisor latch (high byte) - comdiv2: 16-bit fractional baud divide register. the required values for comdiv0, comdiv1 and comdiv2 are derived from the lhsval0, to generate the required baud rate. - comcon0: line control register. once the uart is correctly configured, the lin protocol for receiving and transmitting data is identical to the uart specification. to manage data on the lin bus requires use of the following uart mmrs: - comtx: 8-bit transmit register - comrx: 8-bit receive register - comcon0: line control register - comsta0: line status register to transmit data on the lin bus requires that the relevant data be placed into comtx. to read data received on the lin bus requires the monitoring of comrx. to ensure that data is received or transmitted correctly comsta0 is monitored. for more information please refer to the uart section of the datasheet. under software control it is possible to multiplex the uart data lines (txd and rxd) to external gpio pins (gpio_7 and gpio_8). for more information please refer to the description of the gpio port1 control register (gp1con). 05994-042 13t bit 2t bit 2t bit 2t bit 2t bit >1t bit > = 14t bit 8t bit break sync sta s0 s1 s2 s3 s4 s5 s6 s7 sto protected id figure 42. lin interface timing 05994-043 t break > 13t bit break delimit start bit figure 43. lin break field 05994-044 t bit stop bit start bit figure 44. lin synch byte field 05994-045 id1 id0 start bit stop bit t bit id2 id3 id4 id5 p0 p1 figure 45. lin identifier byte field 05994-046 bit1 bit0 start bit stop bit t bit bit2 bit3 bit4 bit5 bit6 bit7 figure 46. lin data byte field
preliminary technical data aduc7030/aduc7033 rev. pre | page 139 of 150 example lin hardware synchronization routine consider the following c-source code lin initialization routine. void lin_init(void ) { char hvstatus; gp2con = 0x110000; // enable lhs on gpio pins lhscon0 = 0x1; // reset lhs interface do{ hvdat = 0x02; // enable normal lin tx mode hvcon = 0x08; // write to config0 do{ hvstatus = hvcon; } while(hvstatus & 0x1); // wait until command is finished } while (!(hvstatus & 0x4)); // transmit command is correct while((lhssta & 0x20) == 0 ) { // wait until the lhs hardware is reset } lhscon1 = 0x062; // sets stop edge as the fifth falling edge // and the start edge as the first falling // edge in the sync byte lhscon0 = 0x0114; // gates uart rx line, ensure no interference // from the lin into the uart. // selects the stop condition as a falling edge // enables generation of an interrupt on the // stop condition. // enables the interface lhsval1 = 0x03f; // set number of 131khz periods to generate a break interrupt // 0x3f / 131khz ~ 480us which is just over 9.5 tbits. using this configuration, lhsval1 begins to count on the first falling edge received on the lin bus. if lhsval1 exceeds the value written to lhsval1, in this case 0x3f, a break compare interrupt is generated. on the next falling edge, lhsval0 begins counting. lhsval0 monitors the number of falling edges and compares this to the value written to lhscon1[7:4], in this example the number of edges to monitor is the sixth falling edge of the lin frame, or the fifth falling edge of the sync byte. once this number of falling edges is received, a stop condition interrupt is generated. it is at this point that the uart is configured to receive the protected identifier. the uart must not be ungated, via lhscon0[8], before the lin bus returns high. if this occurs, uart communication errors may occur. example code to ensure this is shown below: this process is shown in detail in figure 47. while((gp2dat & 0x10 ) == 0 ) {} // wait until lin bus returns high lhscon0 = 0x4; // enable lhs to detect break condition ungate rx line // disable all interrupts except break compare interrupt irqen = 0x800; // enable uart interrupt // the uart is now configured and ready to be used for lin
aduc7030/aduc7033 preliminary technical data rev. pre | page 140 of 150 05994-047 id1 id0 start bit start bit stop bit stop bit id2 id3 id4 id5 p0 p1 t bit lhsval1 = 0x3f lhsval1 reset and starts counting break compare interrupt generated lhsval0 starts counting lhsval0 stops counting. stop interrupt generated uart configured lhs interrupts disabled except break compare begin receiving data via uart figure 47. example lin configuration lin diagnostics the aduc7030/aduc7033 features the capability to non- intrusively monitor the current state of the lin pin. this read back functionality is implemented via gpio_11. the current state of the lin pin is contained in gp2dat[4] it is also possible to drive the lin pin high and low via user software, allowing the user to detect open circuit conditions. this functionality is implemented via gpio_12. to enable this functionality gpio_12 must be configured as a gpio via gp2con[20]. once configured, the lin pin may be pulled high or low via gp2dat. the aduc7030/aduc7033 also features short circuit protection on the lin pin. if a short circuit condition is detected on the lin pin, hvsta[2] is set. this bit is cleared by re-enabling the lin driver via hvcfg1[3]. it is possible to disable this feature via hvcfg1[2]. lin operation during thermal shutdown when a thermal event occurs, i.e. hvsta[3] is set, and lin communications continues uninterrupted.
preliminary technical data aduc7030/aduc7033 rev. pre | page 141 of 150 bit serial device (bsd) interface bsd is a pulse width modulated signal with 3 possible states: sync, zero and one. these are detailed, along with their associated tolerances, in table 89. the frame length is 19 bits, and communications occurs at 1200bps 3%. table 89. bsd bit level description parameter name min typ max unit tx rate 1164 1200 1236 bits/sec t sync 1/16 2/16 3/16 t period t 0 5/16 6/16 8/16 t period bit encoding t 1 10/16 12/16 14/16 t period bsd communication hardware interface the aduc7030/aduc7033 emulates the bsd communication protocol using a gpio, an irq and the lin synchronization hardware, all of which is under software control 0 5994-048 aduc7030 uart lhs hardware aduc7030 rxd txd bpf internal short-circuit trip reference internal short-circuit sense resistor output disable lin mode hvcfg0[1:0] input voltage threshold reference lin enable (internal pull-up) hvcfg0[5] four lin interrupt sources break lhssta[0] start lhssta[1] stop lhssta[2] break error lhssta[4] vdd rxd enable lhscon0[8] lhsval0 lhsval1 lhs interrupt irqen[7] 5mhz 131khz lhs interrupt logic vdd scr io_vss over voltage protection external lin pin master ecu protection diode master ecu pull-up c load figure 48. bsd i/o hardware interface
aduc7030/aduc7033 preliminary technical data rev. pre | page 142 of 150 bsd related mmrs the aduc7030/aduc7033 emulates the bsd communication protocol using a software (bit bang) interface with some hardware assistance form lin hardware synchronization logic. in effect, the aduc7030/aduc7033 bsd interface uses ? an internal gpio signal (gpio_12) which is routed to the external lin/bsd pin and is controlled directly by software to generate 0s and 1s. ? when reading bits, the lin synchronization hardware, uses lhsval1 to count the width of the incoming pulses so that user code can interpret the bits as sync, 0 or 1 bits. ? when writing bits, again user code toggles a gpio pin and uses the lhscap and lhscmp registers to time pulse widths and generate an interrupt when the bsd output pulse width has reached its required width. the aduc7030/aduc7033 mmrs required for bsd communication are listed below. lhssta: lin hardware sync status register. lhscon0: lin hardware sync control register. lhsval0: lin hardware sync timer 0. 16-bit timer lhscon1: lin hardware sync edge setup register. lhsval1: lin sync break timer. lhscap: lin sync capture register. lhscmp: lin sync compare register. irqen/clr: enable interrupt register fiqen/clr: enable fast interrupt register gp2dat: gpio data register gp2set: gpio set register gp2clr: gpio clear register detailed bit definitions for most of these mmrs have been given previously. in addition to the registers described in the lin section previously, lhscap and lhscmp are new registers, which are required for the operation of the bsd interface. details of these registers follow. lin hardware synchronization capture register: name: lhscap address: 0xffff0794 default va lu e: 0x0000 access: read only function: the 16-bit read only lhscap register holds the last captured value of the internal lin synchronization timer (lhsval0). in bsd mode, the lhsval0 is clocked directly from an internal 5mhz clock, its value is loaded into the capture register on every falling edge of the bsd bus lin hardware synchronization compare register: name: lhscmp address: 0xffff0798 default va lu e: 0x0000 access: read/write function: the lhscmp register is used to time bsd output pulse widths. once enabled via lhscon0[5], a lin interrupt is generated when the value in lhscap equals the value written in lhscmp. this functionality allows user code determine how long a bsd transmission bit (sync, 0 or 1) should be asserted on the bus
preliminary technical data aduc7030/aduc7033 rev. pre | page 143 of 150 bsd communications frame to transfer data between a master and slave, or visa versa, requires the construction of a bsd frame. a bsd frame contains seven key components, pause/synch, direction bit, the slave address, the register address, data, parity bits one and two and the acknowledge from the slave. if the master is transmitting data, then all bits, except the ack, are transmitted by the master. if the master is requesting data from the slave, the master transmits the pause/synch, the direction bit, slave address, register address and p1 bits. the slave then transmits the data bytes, parity bit 2 and the ack. pause: >= 3 synchronization pulses dir: signifies the direction of data transfer zero if master sends request one if slave sends request slave address register address: defines register to be read or written bit 3 is set to write, cleared to read data: 8-bit read only receive register p1 and p2 p1 = "0" if even number of "1" in 8 previous bits p1 = "1" if odd number of "1" in 8 previous bits p2 = "0" if even number of "1" in data word p2 = "1" if odd number of "1" in data word ack: zero if transmission is successful. the ack is always transmitted by the slave to indicate if the information was received or transmitted. table 90. bsd protocol description pause dir slave address register address p1 data p2 ack 3 bits 1 bit 3 bits 4 bits 1 bit 8 bit 1 bit 1 bit bsd example pulse widths an example of the different pulse widths is shown in figure 49. for each bit the period for which the bus is held low defines what type of bit it is. if the bit is a synch bit, the pulse is held low for 1 bit. if the bit is a zero bit, the pulse is held low for 3 bits. if the bit is a one bit, the pulse is held low for 6 bits. if the master is transmitting data, the signal is held low for the duration of the signal by the master. an example of a master transmitting zero is shown in figure 50. if the slave is transmitting data, the master pulls the bus low to begin communications. the slave must then pull the bus low before t sync elapses and hold the bus low until either t zero or t one has elapsed, after which the bus is released by the slave. an example of a slave transmitting a zero is shown in figure 51. 0 5994-049 t sync t zero t 1 figure 49. bsd bit transmission 05994-050 bus pulled low by master t sync bus released by master after t zero t zero figure 50. bsd master transmitting zero 0 5994-051 bus pulled low by master bus released by slave after t zero bus held low by slave released by master t sync t zero figure 51. bsd slave transmitting zero typical bsd program flow as bsd is a pwm communications protocol controlled by software, it is necessary for the user to construct the required data from each bit. for example the slave address. the slave node receives the three bits and constructs the relevant address. when bsd communication is initiated by the master, data is transmitted and received by the slave node. a flow diagram showing this process is shown in figure 52.
aduc7030/aduc7033 preliminary technical data rev. pre | page 144 of 150 05994-052 transmit data to master transmit second parity bit receive data from master receive second parity bit receive synchronization pulses receive direction bit receive slave address receive register address receive first parity bit transmit ack/nack initialize bsd hardware/ software figure 52. bsd slave node state machine bsd data reception to receive data, the lin/bsd peripheral must first be configured in bsd mode lhscon[6]=1. in this mode lhscon0[8] should be set to ensure the lhs break timer (see lhsval1) will generate an interrupt on the rising edge of the bsd bus. the lhs break timer is cleared and starts counting on the falling edge of the bsd bus and is subsequently stopped and generates an interrupt on the rising edge of the bsd bus. given the lhs break timer is clocked by the low power (131khz) oscillator, the value in lhsval1 can be interpreted by user code to determine if the received data bit is a bsd sync pulse, 0 or 1. 05994-053 bsd ?0? period bsd ?1? period lhsval1 cleared and starts counting on this edge 1 lhsval1 stopped and generates interrupt on this edge 2 figure 53. master transmit, slave read bsd data transmission user code forces a gpio signal (gpio_12) low for a specified time to transmit data in bsd mode. in addition user code will also use the sync timer(lhsval0), lhs sync capture register(lhscap) and the lhs sync compare register(lhscmp) to time how long the bsd bus should be held low for 0 or 1 bit transmissions. as described earlier, even when the slave is transmitting, the master will always start the bit transmission period by pulling the bsd bus low. if bsd mode is selected (lhscon0[6]=1), then the lin sync timer value will be captured in lhscap on every falling edge of the bsd bus. the lin sync timer is running continuously in bsd mode. user code can then immediately force gpio_12 low and reads the captured timer value from lhscap. a calculation of how many (5mhz) clock periods should elapse before the gpio_12 should be driven high for a 0 or 1 pulse width can be made. this number can be added to the lhscap value and written into the lhscmp register. if lhscon0[5] is set, the sync timer which continues to count (being clocked by a 5mhz clock) will eventually equal the lhscmp value and generate an lhs compare interrupt(lhssta[3]). the response to this interrupt should be to force the gpio_12 signal (and therefore, the bsd bus) high. the software control of the gpio_12 signal along with the correct use of the lin synchronization timers ensures that valid 0 and 1 pulse widths can be transmitted from the aduc7030/aduc7033 as shown in figure 42 below. again care needs to be taken if switching from bsd write mode to bsd read mode as described in lhscon0[8]. 05994-054 bsd ?0? period bsd ?1? period lhsval0 loaded into lhscap here 2 master drives bsd bus low 1 software asserts bsd low here 3 software de-asserts bsd high here 5 lhscmp = lhsval0 interrupt generated here 4 figure 54. master read, slave transmit wake-up from bsd interface the mcu core can be woken up from power-down via the bsd physical interface. before entering power-down mode, user code should enable the start condition interrupt (lhscon0[3]) once this interrupt is enabled, a high to low transition on the lin/bsd pin will generate an interrupt event and wake up the mcu core.
preliminary technical data aduc7030/aduc7033 rev. pre | page 145 of 150 aduc7030/aduc7033 on-chip diagnostics the aduc7030/aduc7033 integrates multiple diagnostic support circuits on-chip. these circuits allow the device to test core digital functionality, analog front-end and high-voltage i/o ports in-circuit. adc diagnostics internal test voltage the current channel can be configured to convert on an internal 8.3mv test voltage. on any gain range the result should be within 0.5% of the expected result. internal short mode the current and voltage input channels can also be shorted internally. converting on the internal short will allow an assessment of the internal adc noise to be determined. internal current sources internal current sources can also be enabled on both current and temperature channels. these current sources can be used to determine external short or open circuit conditions in both external shunt or temperature sensor configurations. high voltage i/o diagnostics high voltage i/o read back all high voltage i/o pins will be supported with read back capability. this will allow detection of external short conditions. high voltage current detection all high voltage i/o pins will also have a high current detection capability allowing high side connections to vbat to be detected and controlled.
aduc7030/aduc7033 preliminary technical data rev. pre | page 146 of 150 part identification two registers mapped into the mmr space are intended to allow user code identify and trace, manufacturing lot id information, part id number, silicon mask revision and kernel revision. this information is contained in the sysser0 and sysser1 mmr, which are described in detail below. system serial id register 0: name: sysser0 address: 0xffff0238 default value: 0x00000000 (updated by kernel at power-on) access: read/write function: at power-on, this 32-bit register will hold the value of the original manufacturing lot number from which this specific aduc7030/aduc7033 unit was manufactured (b ottom die only). used in conjunction with sysser1, this lot number will allow the full manufacturing history of this part to be traced (bottom die only) table 91. sysser0 mmr bit descriptions bit description 31- 27 wafer number: the 5 bits read from this location will give the wafer number (1-24) from the wafer fabrication lot id which this device came f rom, and when used in conjunction with sysser0[26- 0] provides individual wafer traceability. 26- 22 wafer lot fabrication plant the 5 bits read from this location reflec t the manufacturing plant associate with this wafer lot, and used in conjunction with sysser0[21-0] provides wafer lot traceability. 21- 16 wafer lot fabrication id the 6 bits read from this loca tion form part of the wafer lot fabrication id, and used in conjunction with sysser0[26-22] and sysser0[15-0] provides wafer lot traceability. 15-0 wafer lot fabrication id these 16 lsbs will hold a 16-bit number, which should be interp reted as the wafer fabrication lot id number. when used in conjunction with the value in sysser1 i.e. the manufacturing lot id, this number is a unique identifier for the part. for full traceability, part assembly lot number, sysser0 and module number need to be recorded. the lot number is part of the branding on the package as shown table 92: table 92. branding example lfcsp lfqfp line 1 aduc7033 aduc7033 line 2 bcpz 8w bstz 8w line 3 a40 #date code a40 #date code line 4 assembly lot number assembly lot number
preliminary technical data aduc7030/aduc7033 rev. pre | page 147 of 150 system serial id register 1: name: sysser1 address: 0xffff023c default value: 0x00000000 (updated by kernel at power-on) access: read/write function: at power-on, this 32-bit register will hold the values of the part id number, silicon mask revision number and kernel revision number (bottom die only) as detailed below table 93. sysser1 mmr bit descriptions bit description 31-28 silicon mask revision id the 4 bits read from this nibble reflect th e silicon mask id number. specifically, the hex value in this nibble should be decod ed as the lower hex nibble in the hex numbers reflecting the ascii characters in the range a to o. examples: bits 19-16 = 0001 = 1hex, therefore this value should be interpre ted as 41 which is ascii character a corresponding to silicon mask revision a bits 19-16 = 1011 = bhex, therefore the number is interpreted as 4b which is ascii character k corresponding to silicon mask revision k the allowable range for this value is 1 to 15 wh ich is interpreted as 41 to 4f or a to o) 27-20 kernel revision id this byte contains the hex number, which should be interpreted as an ascii character indicating the revision of the kernel firmware embedded in the on-chip flash/ee memory. example: reading 0x41 from this byte should be interpre ted as a indicating a revision a kernel is on-chip. 19-16 kernel minor revision number for preproduction release, these bits refer to the devices kernel minor revision number 15-0 part id these 16 lsbs will hold a 16-bit number, which should be interprete d as the part id number. when used in conjunction with the value in sysser0 i.e. the manufacturing lot id, th is number is a unique identifier for the part. system kernel checksum: name: syschk address: 0xffff0240 default value: 0x00000000(updated by kernel at power-on) access: read/write function: at power-on, this 32-bit register will hold the kernel checksum
aduc7030/aduc7033 preliminary technical data rev. pre | page 148 of 150 system identification fee0adr: name: fee0adr address: 0xffff0e10 default value: non zero access: read/write function: this 16-bit register dictates the address upon which any flash/ee command executed via fee0con will act upon note: this mmr is also used to identify aduc7030 fa mily member and pre-release silicon revision table 94. fee0adr system identi fication mmr bit descriptions bit description 15-12 reserved 11-8 reserved silicon revision 0x0 type6 0x1 type6x 0x4 type7y 0x5 type7op 0x6 type8 0x7 type7op1 0x8 type7m 0x9 type7 0xa type8w 0xb type9 0xc type7ml 0xd type8v 7-4 others reserved 3-0 aduc703x family id 0x0 aduc7030 0x1 aduc7031 0x2 aduc7032 0x3 aduc7033 others reserved
preliminary technical data aduc7030/aduc7033 rev. pre | page 149 of 150 aduc7030/aduc7033 example schematic 05994-055 ground connected to the negative terminal of the battery figure 55. schematic this example schematic represents a basic functional circuit implementation. additional components may need to be added based o n your use of the part. for a more detailed discussion on circuit implementation and layout please refer to the application note layout and board recommendation .
aduc7030/aduc7033 preliminary technical data rev. pre | page 150 of 150 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 56. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 figure 57. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model temperature range package description package option ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr05994-0-10/06(pre)
aduc7030: integrated precision batt ery sensor for automotive the aduc7030 is a comp lete, system solution for battery monitoring in 12v automotive applications. the device integrates all of the required features to precisely and intelligently monitor, process ... more this product is no longer sampling. the recommended replacement is aduc7034 . on this page: resources features diagrams explore other products pricing, packaging & availability quick links lead(pb) - free data application notes evaluation boards/tools resources overview product reviews rarely asked questions seminars & webcasts solutions bulletins third party developers pa g e 1 of 3 analo g devices: aduc7030: inte g rated precision batter y sensor for automotive :: analo g microcontrollers 14-jul-2008 htt p ://www.analo g .com/en/analo g -microcontrollers/aduc7030/ p roducts/ p roduct.html
features dual channel, simultaneous sampling, 16-bit ? adcs 5ppm/c voltage reference 20mhz arm7tdmi core 20mhz arm7tdmi core 20mhz arm7tdmi core lin 2.0 (slave) in-system serial programming in-system jtag emulation diagrams enlar g es y mbols and foot p rints functional block diagram for aduc7030 explore other products new products similar products aduc7060 - low-power, precision analog microcontroller, dual - ? adcs, flash/ee, arm7tdmi aduc7061 - low-power, precision analog microcontroller, dual - ? adcs, flash/ee, arm7tdmi pa g e 2 of 3 analo g devices: aduc7030: inte g rated precision batter y sensor for automotive :: analo g microcontrollers 14-jul-2008 htt p ://www.analo g .com/en/analo g -microcontrollers/aduc7030/ p roducts/ p roduct.html
aduc7033 - integrated precision battery sensor for automotive aduc7030 - integrated precision battery sensor for automotive more subscribe to new products feed aduc7030 model options pricing, packaging & availability print table model status package pins temp. range price* (1000 pcs.) available rohs compilant samples cart purchase cart aduc7030bcpz-8v prodn 48 ld lfcsp 7x7mm (5.25ep) 48 ind $6.29 07/11/2008 y material declaration add to cart add to cart aduc7030bcpz- 8v-rl prodn 48 ld lfcsp 7x7mm (5.25ep) 48 ind $6.29 08/29/2008 y material declaration contact adi add to cart the usa list pricing shown is for budgetary use on ly, shown in united states dollars (fob usa per unit for the stated volume), and is subject to change. international prices may differ due to local duties, taxes, fees and exchange rates. for volume-specific price or delivery quotes, please contact yo ur local analog devices, inc. sales office or authorized distributor. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view sales and distribution offices view samples cart view purchase cart pa g e 3 of 3 analo g devices: aduc7030: inte g rated precision batter y sensor for automotive :: analo g microcontrollers 14-jul-2008 htt p ://www.analo g .com/en/analo g -microcontrollers/aduc7030/ p roducts/ p roduct.html
aduc7033: integrated precision batt ery sensor for automotive the aduc7033 is a comp lete, system solution for battery monitoring in 12v automotive applications. the device integrates all of the required features to precisely and intelligently monitor, process ... more aduc7033 silicon anomaly sheet available this anomaly list describes the known b ugs, anomalies, workarounds, and planned feature enhancements for the aduc702x microconverter?. on this page: data sheet resources features diagrams specifications explore other products pricing, packaging & availability quick links data sheet rev a, 03/2008 , (pdf, 111 kb) more (about data sheets) lead(pb) - free data application notes evaluation boards/tools resources overview product reviews rarely asked questions seminars & webcasts solutions bulletins third party developers pa g e 1 of 4 analo g devices: aduc7033: inte g rated precision batter y sensor for automotive :: analo g microcontrollers 14-jul-2008 htt p ://www.analo g .com/en/analo g -microcontrollers/aduc7033/ p roducts/ p roduct.html
features dual channel, simultaneous sampling, 16-bit ? adcs 5ppm/c voltage reference 20mhz arm7tdmi core 96kb flash/ee memory 6kb sram lin 2.0 (slave) in-system serial programming in-system jtag emulation diagrams enlar g eothe r dia g rams s y mbols and foot p rints functional block diagram for aduc7033 specifications mcu core arm7 tdmi flash (kbytes) 0 sram (bytes) 0 gpio pins 9 resolution (bits) 16bit temperature range (c) -40 to 85 pa g e 2 of 4 analo g devices: aduc7033: inte g rated precision batter y sensor for automotive :: analo g microcontrollers 14-jul-2008 htt p ://www.analo g .com/en/analo g -microcontrollers/aduc7033/ p roducts/ p roduct.html
explore other products new products similar products aduc7030 - integrated precision battery sensor for automotive aduc7061 - low-power, precision analog microcontroller, dual - ? adcs, flash/ee, arm7tdmi aduc7033 - integrated precision battery sensor for automotive aduc7034 - integrated precision battery sensor for automotive more subscribe to new products feed aduc7033 model options pricing, packaging & availability print table model status package pins temp. range price* (1000 pcs.) available rohs compilant samples cart purchase cart aduc7033bcpz-8l prodn 48 ld lfcsp 7x7mm (5.25ep) 48 ind $6.64 10/10/2008 y material declaration add to cart add to cart aduc7033bcpz- 8l-rl prodn 48 ld lfcsp 7x7mm (5.25ep) 48 ind $6.64 07/11/2008 y material declaration contact adi add to cart aduc7033bstz-8l prodn 48 ld lqfp 48 ind $6.64 01/23/2009 y material declaration add to cart add to cart aduc7033bstz- 8l-rl prodn 48 ld lqfp 48 ind $6.64 10/17/2008 y material declaration contact adi add to cart eval- aduc7033qspz prodn evaluation boards - tbd $249.00 09/05/2008 y contact adi add to cart pa g e 3 of 4 analo g devices: aduc7033: inte g rated precision batter y sensor for automotive :: analo g microcontrollers 14-jul-2008 htt p ://www.analo g .com/en/analo g -microcontrollers/aduc7033/ p roducts/ p roduct.html
the usa list pricing shown is for budgetary use on ly, shown in united states dollars (fob usa per unit for the stated volume), and is subject to change. international prices may differ due to local duties, taxes, fees and exchange rates. for volume-specific price or delivery quotes, please contact yo ur local analog devices, inc. sales office or authorized distributor. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view sales and distribution offices view samples cart view purchase cart pa g e 4 of 4 analo g devices: aduc7033: inte g rated precision batter y sensor for automotive :: analo g microcontrollers 14-jul-2008 htt p ://www.analo g .com/en/analo g -microcontrollers/aduc7033/ p roducts/ p roduct.html

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